Abstract: An Ethernet networking system is disclosed. The system includes a first network device having an interface to receive Ethernet data from a first Ethernet source. An Ethernet media converter couples the network device to telephone wires. The Ethernet media converter includes a first Ethernet transceiver PHY integrated circuit (IC) having a first system-side interface for coupling to a first transmission media including multiple pairs of wires and a first line-side interface. The Ethernet media converter further includes a second Ethernet transceiver PHY IC having a second line-side interface connected to the first line-side interface, and a second system-side interface for coupling to the telephone wires.

Abstract: An integrated circuit (IC) chip includes transceiver circuitry. The transceiver circuitry includes a differential transmit circuit and a hybrid circuit. The differential transmit circuit includes a first transmit path for transmitting first data of a first polarity to a transmission line. A second transmit path generates replica first data having a second polarity opposite the first polarity. The hybrid circuit includes a first input path coupled to the second transmit path. A second input path is coupled to the transmission line for receiving a first summed signal including the first data and second data. The second data is received from the transmission line simultaneous with transmission of the first data along the transmission line. An output circuit generates an output representing a summation of the replica first data and the first summed signal.

Abstract: A method of operation in an Ethernet transceiver is disclosed. The method includes initiating a training mode of operation, and transmitting Infofield frames to a link partner. Each Infofield frame including a payload field to provide data to the link partner. A flow of the transmitted Infofield frames is controlled such that a new Infofield frame is not transmitted before a previous Infofield frame is received by the link partner.

Abstract: A Serializer/Deserializer (SERDES) circuit is disclosed. The circuit includes an input/output (I/O) pad for coupling to a duplex SerDes link. An adjustable delay line provides a first component of a relative phase between a receive signal sampling point and a transmit echo signal. A second delay circuit generates a second component of the relative phase. A timing relationship between the receive signal sampling point and the transmit echo signal is based on the sum of the first and second components.

Abstract: A method of transmitting Ethernet data over multiple physical sub-channels is disclosed. The method includes determining one or more noisy sub-channels affected by alien crosstalk; selectively reducing a number of data bits per symbol for transmitted data symbols along the noisy sub-channels; transmitting data along the noisy sub-channels via sparser constellations; and transmitting data along non-noisy sub-channels via denser constellations.

Abstract: A method of signaling between Ethernet transceivers along a link is disclosed. The method includes advertising first and second supported data rates between the transceivers during an autonegotiation sequence. The link is then trained to train transceiver operating parameters with a training sequence of symbols. The training includes initiating the training sequence to support the first data rate, determining whether the link can operate at the first data rate, and transferring control information requesting a retrain at a second data rate different than the first data rate if the link cannot support the first data rate. The link is retrained, in response to the control information, to train the parameters for operation at the second data rate. The retraining is carried out without repeating the autonegotiation sequence. The link is then operated in a data transfer mode at the second data rate.

Abstract: A serializer-deserializer (SerDes) integrated circuit (IC) chip includes a first SerDes receiver circuit having a first input for coupling to a first SerDes link, and a first output. A second SerDes receiver circuit has a second input for coupling to a second SerDes link. The second SerDes receiver circuit includes a second output. Crosstalk filter circuitry is disposed between the first SerDes receiver circuit and the second SerDes receiver circuit.

Abstract: A method for characterizing alien crosstalk between an aggressor link and a victim link is disclosed. The method includes operating a transmit transceiver coupled to the aggressor link in a transmit mode of operation. A receive transceiver is coupled to the victim link in a receive mode of operation. Using the receive transceiver, a parameter is measured that is associated with alien crosstalk due to transmissions from the aggressor link.

Abstract: A method of operation in a system is disclosed. The system includes a system processor, main memory coupled to the system processor, and a serial input/output (IO) interface coupled to the processor. The method includes de-framing multi-media packet data with a local area network peripheral device such as Ethernet, the multi-media packet data having a timing reference. The packet data is mapped to the main memory with the Ethernet peripheral device. The multi-media packet data is then transferred to the main memory as multi-media data, and stored in storage locations of the main memory in accordance with the mapping. The mapping information is accessed from device Host operating system with a second peripheral device via the serial I/O interface. The second peripheral device directly accesses the main memory storage locations. Significant power savings is realized for the CPU.

Abstract: A method for determining a power back-off value for an Ethernet channel is disclosed. The method includes measuring a signal-to-noise ratio (SNR) for each of the channels with a receiver corresponding to each channel. A transmit power level for a link partner transmitter is determined, where the transmit power level represents a minimum power level at the link partner transmitter that results in the measured SNR value at the receiver satisfying a predetermined SNR threshold. The transmit power level is communicated to the link partner transmitter and Ethernet data is then transceived between the link partners based on the determined transmit power level.

Abstract: Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.

Abstract: An Ethernet adapter module for interfacing a network endpoint device to an Ethernet network is disclosed. The Ethernet adapter module includes an Ethernet medium access controller (MAC) and an Ethernet physical layer device (PHY). The Ethernet MAC includes a processor and Time Sensitive Networking and/or Audio Video Bridging (TSN/AVB) state machines that cooperate with the processor to (1) identify a TSN/AVB request from the network endpoint device, and (2) discover a network topology along which to transfer data between the network endpoint device and a second network endpoint device in accordance with a predetermined Quality of Service (QoS). The Ethernet PHY is coupled to the Ethernet MAC and includes timestamp logic to apply a timing reference to the data being transferred.

Abstract: An Ethernet adapter module for interfacing a network endpoint device to an Ethernet network is disclosed. The Ethernet adapter module includes an Ethernet medium access controller (MAC) and an Ethernet physical layer device (PHY). The Ethernet MAC includes a processor and audio video bridging (AVB) state machines that cooperate with the processor to (1) identify an AVB request from the network endpoint device, and (2) discover a network topology along which to transfer data between the network endpoint device and a second network endpoint device in accordance with a predetermined Quality of Service (QoS). The Ethernet PHY is coupled to the Ethernet MAC and includes timestamp logic to apply a timing reference to the data being transferred.

Abstract: A method of detecting a fault in an Ethernet system is disclosed. The system includes multiple physical channels, each channel bounded by a pair of link partner transceivers. The method includes selectively coupling at least a first one of the physical channels to a second one of the physical channels. A test pattern is then transmitted along the first and second physical channels. Cross-channel information corresponding to the transmitted test pattern is received. An echo canceller in the second of the multiple channels is trained to generate an impulse response corresponding to the received crosstalk information. For a selected segment of the system, the generated impulse response is compared to an expected impulse response for that selected segment. The determination of whether a fault exists is based on the comparison.

Abstract: Cancellation of alien interference in signals transmitted over communication channels. In one aspect, one or more signals are received at a receiver from a communication link, an alien interference in the received signals is determined based on at least one of the received signals, one or more canceling signals is determined based on the alien interference, and the canceling signals are used to reduce the alien interference in the one or more received signals.

Abstract: An Ethernet transceiver integrated circuit (IC) chip is disclosed. The IC chip includes multiple physical sub-channels, where each sub-channel transfers data symbols along a wired link. Each data symbol representing a group of multiple data bits. Logic determines a signal quality parameter value for each of the sub-channels. For each sub-channel, in a first mode where a given sub-channel exhibits a signaling quality above a first predetermined threshold, the logic assigns a modulation of a first type associated with a first constellation. In a second mode where a given sub-channel exhibits a signaling quality below the first predetermined threshold, the logic assigns a modulation of a second type associated with a second constellation that is sparser than the first constellation.

Abstract: A 10GBASE-T circuit is disclosed. The circuit includes a physical (PHY) integrated circuit and a media access control (MAC) integrated circuit. The PHY couples to a data transfer medium and carries out data transfers at a PHY data rate. The MAC integrated circuit controls access to the date transfer medium and couples to the PHY via a bidirectional link operating at a MAC data rate. Rate control logic detects the PHY data rate, and adjusts the MAC data rate to the PHY data rate. Changes to the PHY and MAC data rates may be made at rates higher than 1 Gbps.

Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and logic to aggregate the Ethernet block data bits in accordance with a 512/513B code. A forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits.

Abstract: A method of operation in an Ethernet transceiver is disclosed. The method includes initiating a training mode of operation, and transmitting Infofield frames to a link partner. Each Infofield frame including a payload field to provide data to the link partner. A flow of the transmitted Infofield frames is controlled such that a new Infofield frame is not transmitted before a previous Infofield frame is received by the link partner.

Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate, logic to associate the Ethernet block data bits with an auxiliary bit and a number of Reed-Solomon check bytes, and a forward error correction encoder. The encoder is coupled to the logic to encode all of the data bits, auxiliary bit and the Reed-Solomon check bytes into a first error encoded transport frame having plural error check bits. A symbol mapper receives the first error encoded transport frame and modulates the first error encoded transport frame into symbols, each of the symbols having uncoded bits. A BASE-T transmitter is coupled to the symbol mapper to transmit the first group of symbols over an Ethernet link at one of a selection of symbol rates. Errors in the uncoded bits are correctable via the Reed-Solomon check bytes.