Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

Abstract: Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.

Abstract: A system and method are disclosed for a cache IP that includes registers that are programmed through a service port. Service registers are selected from the registers to define an address range so that all cache lines within the address range can be flushed automatically using a control signal sent to a control register.

Abstract: A Network-on-Chip (NoC) link with an upstream bypassable narrowing serialization adapter and a downstream bypassable widening serialization adapter, which are able to heal a link, without losing throughput, by using one or a small number of sideband signals to bypass individual known-bad wires. The serialization adapters are normally bypassed. To avoid sending information on broken wires, bypassing is disabled so that information is serialized to only a portion of the link. Serialization can be applied to any portion of a link down to as little as one bit wire.

Abstract: A system and method for detecting writes of data to errant locations in storage arrays. Address information and information redundant with address information is encoded and stored in proximity with data. Upon reading the stored data, the corresponding address information is decoded and compared to the address of the intended read. A mismatch indicates a possible write to an errant location.

Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.

Abstract: A system and method are disclosed with the ability to track usage of information and determine commonly used patterns to be stored and updated in a directory. The information includes counter values that represent the frequency of occurrence of a pattern that is committed to the directory. Thus, allows the system to control and reduce the size allocated to storing information in the directory because the size is reduced by limiting address bits. This, in turn, creates additional benefits in speed and power because it allows subsystems to avoid transmitting, storing, and operating upon excessive address information.

Abstract: A system and method are disclosed with the ability to track usage of information, which patterns, and determine the most frequently used patterns to be stored and updated in a directory, thereby controlling and reducing the size allocated to storing information in the directory. The size is reduced by limiting address bits thereby allowing subsystems to avoid transmitting, storing, and operating upon excessive address information.

Abstract: Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.

Abstract: A system and method for estimating a floorplan designs based on feedback to machine learning algorithms to accumulate data for improving future floorplan design estimates and reducing design time.

Abstract: A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate.

Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.

Abstract: A Network-on-Chip (NoC) link with an upstream bypassable narrowing serialization adapter and a downstream bypassable widening serialization adapter. The serialization adapters are normally bypassed. To avoid sending information on broken wires, bypassing is disabled so that information is serialized to only a portion of the link. Serialization can be applied to any portion of a link down to as little as one bit wire.

Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.

Abstract: A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.

Abstract: In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.

Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.

Abstract: A system and method are disclosed that include recovery of the system directory when an uncorrectable error is detected. According to the various aspects and embodiments of the invention, the system and method disclosed can manage single bit error detection and two-bit error detection.

Abstract: A system and method are disclosed that include a bridge that translates non-coherent transactions, which are received from a non-coherent subsystem, into one or more coherent transactions to be issued to a coherent subsystem. The bridge also buffers data coherently in an internal cache, also known as a proxy cache, based on certain attributes of the non-coherent transaction. The invention may be applied to any cache, which receives read and write transactions that become coherent transactions.

Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents.