Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a die attach pad and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die attach pad are all covered with a molding material, with portions of the electrical contacts and die attach pad protruding from a bottom surface of the molding material.

Abstract: A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers is deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.

Abstract: A method of fabricating an integrated circuit package. The method includes providing a first leadframe and a second leadframe, laminating the second leadframe to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and mounting a semiconductor die on another portion of the first leadframe.

Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.

Abstract: A process for fabricating a leadless plastic chip carrier includes providing a leadframe including a plurality of contacts circumscribing a void; fixing a heat sink to the contacts of the leadframe using an intermediate non-electrically conductive adhesive such that the heat sink spans the void; mounting a semiconductor die to the heat sink in the void; wire bonding ones of the contacts to the pads of the semiconductor die; encapsulating the semiconductor die and the wire bonds in a molding material and singulating the leadless plastic chip carrier.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a leadframe strip to define a die attach pad and at least one row of contact pads; mounting a semiconductor die to one side of the leadframe strip, on the die attach pad; wire bonding the semiconductor die to ones of the contact pads; releasably clamping the leadframe strip in a mold by releasably clamping the contact pads; molding in a molding compound to cover the semiconductor die, the wire bonds and a portion of the contact pads not covered by the clamping; releasing the leadframe strip from the mold; depositing a plurality of external contacts on the one side of the leadframe strip, on the contact pads, such that the external contacts protrude from the molding compound; mounting at least one of an active and a passive component to a second side of said leadframe strip; and singulating to provide the integrated circuit package.

Abstract: An integrated circuit package is provided. The package includes a die attach pad having a first side and a second side. A first semiconductor die is mounted to the first side of the die attach pad, a plurality of contact pads disposed in close proximity to the first semiconductor die. A first plurality of wire bonds connect the first semiconductor die and ones of the contact pads. An overmold encapsulates the first plurality of wire bonds and the first semiconductor die, the die attach pad and the contact pads being embedded in the overmold. A plurality of leads are disposed proximal the second side of the die attach pad. A second semiconductor die is mounted to one of the second side of the die attach pad and ones of the plurality of leads such that the ones of the plurality of leads are electrically connected to the second semiconductor die. The second semiconductor die and the leads are embedded in an encapsulant. The die attach pad shields the second semiconductor die.

Abstract: A process for manufacturing an integrated circuit package includes forming a plurality of solder balls on a first surface of a substrate and mounting a semiconductor die to the substrate such that bumps of the semiconductor die are electrically connected to conductive traces of the substrate. The semiconductor die and the solder balls are encapsulated in an overmold material on the substrate such that portions of the solder balls are exposed. A ball grid array is formed such that bumps of the ball grid array are electrically connected to the conductive traces and the integrated circuit package is singulated.

Abstract: A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding material in a mold, the semiconductor die and the contacts are molded in the molding material, between the metal carrier and a metal strip. The metal carrier and the metal strip are etched away and the integrated circuit package is singulated.

Abstract: A process for fabricating an integrated circuit package. Metal is plated up on a substrate to provide a plurality of contact pads and a plurality of fiducial markings on a periphery of the contacts. A transparent mask is selectively deposited on the substrate, over the fiducial markings. A semiconductor die is mounted on the substrate such that the contact pads circumscribe the semiconductor die and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds are encapsulated and the semiconductor die and contact pads are covered in a molding material. The substrate is selectively etched to thereby etch away the substrate underneath the contact pads and the semiconductor die. The integrated circuit package is singulated from other integrated circuit packages by sawing using the fiducial markings.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A cavity-down ball grid includes a flexible circuit tape including a flexible tape laminated to a conductor layer. The flexible circuit tape has an aperture therein. A thermally conductive heat spreader is fixed to a first surface of the flexible circuit tape and the heat spreader has a cavity aligned with the aperture of the flexible circuit tape. A semiconductor die is mounted to the heat spreader in a die-down configuration in the cavity. A thermally conductive die adapter is fixed to the semiconductor die such that a portion of the die adapter protrudes from the cavity. A plurality of wire bonds connect the semiconductor die to bond sites on the second surface of the flexible circuit tape. An encapsulating material encapsulates the semiconductor die and the wire bonds and a plurality of solder balls are disposed on a second surface of the flexible circuit tape, in the form of a ball grid array.

Abstract: A ball grid array package is manufactured by mounting a semiconductor die to a first surface of a substrate and mounting a die adapter to the semiconductor die. The semiconductor die is wire bonded to ones of conductive traces of the substrate. A collapsible spacer is mounted to the substrate and the substrate is releasably clamped to an upper side of a mold cavity. A heat spreader and at least one collapsible spacer are placed in the mold cavity such that the collapsible spacer is disposed between the heat spreader and the substrate. A molding compound is molded in the mold, thereby molding the semiconductor die, the substrate, the wire bonds, the die adapter, the at least one collapsible spacer and the heat spreader into the molding compound to provide a molded package. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

Abstract: A process for fabricating a leadless plastic chip carrier includes selectively depositing a plurality of base layers on a first surface of a base of a leadframe strip to at least partially define a die attach pad and at least one row of contact pads. At least one further layer is selectively deposited on portions of the plurality of layers to further define at least the contact pads. The leadframe strip is then treated with a surface preparation. A semiconductor die is mounted to the die attach pad, followed by wire bonding the semiconductor die to at least the contact pads. Molding the semiconductor die, the wire bonds, the die attach pad and the contact pads on the surface of the leadframe strip, in a molding compound follows. The leadframe strip is etched to expose the contact pads and the die attach pad and the leadless plastic chip carrier is singulated from a remainder of the leadframe strip.

Abstract: A process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts. A semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts. The second side of the leadframe strip is encapsulating, including the semiconductor die and wire bonds, in a molding material. The carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.

Abstract: A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side of the contact pads and the dielectric material, applying a second metal layer on the metal seed layer, selectively etching the second metal layer and the metal seed layer to provide pad frame circuitry, and building up metal on selective portions of the pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, the die connect pads being electrically connected to the contact pads by the pad frame circuitry.

Abstract: A process for fabricating a leadless plastic chip carrier includes laminating a first metal strip to a second metal strip to form a leadframe strip, selectively etching the first metal strip to define at least a row of contact pads, mounting a semiconductor die to either a die attach pad or the second metal strip and wire bonding the semiconductor die to ones of the contact pads, encapsulating a top surface of the leadframe strip in a molding material, removing the second metal strip, thereby exposing the die attach pad and the at least one row of contact pads, and singulating the leadless plastic chip carrier from the leadframe strip.

Abstract: A flip-chip ball grid array integrated circuit package with improved thermo-mechanical properties is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. A semiconductor die is flip-chip mounted to the first surface of the substrate and electrically connected to ones of the conductive traces. An intermetallic heat spreader is fixed to a back side of the semiconductor die and a plurality of contact balls are disposed on the second surface of the substrate. The contact balls are in the form of a ball grid array and ones of the contact balls of the ball grid array are electrically connected to ones of the conductive traces.