Patents Assigned to Asat Ltd.
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Patent number: 6818472Abstract: An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die. A plurality of wire bonds connect the semiconductor die to the conductive traces of the substrate and an overmold material covers the first surface of the substrate and a remainder of the semiconductor die. A ball grid array is disposed on the second surface of the substrate. Bumps of the ball grid array are in electrical connection with the conductive traces.Type: GrantFiled: February 24, 2003Date of Patent: November 16, 2004Assignee: Asat Ltd.Inventors: Chun Ho Fan, Joseph Andrew Martin, Ming Wang Sze, Tak Sang Yeung
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Patent number: 6818978Abstract: An integrated circuit package is provided. The package has a substrate having first and second surfaces and a plurality of conductive traces therebetween. A stacked semiconductor die apparatus is coupled to the substrate. The stacked semiconductor die apparatus includes a first semiconductor die, a second semiconductor die stacked on the first semiconductor die and a shield disposed between the first and second semiconductor dice. A plurality of wire bonds connect the first and second semiconductor dice to ones of the conductive traces of the substrate. At least one encapsulating material encapsulates the wire bonds, the first semiconductor die and the second semiconductor die. A ball grid array is disposed on the second surface of the substrate such that bumps of the ball grid array are in electrical connection with ones of the conductive traces.Type: GrantFiled: November 19, 2002Date of Patent: November 16, 2004Assignee: Asat Ltd.Inventor: Chun Ho Fan
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Patent number: 6818980Abstract: An integrated circuit package includes a substrate having conductive traces therein. A first semiconductor die is mounted in a die-down configuration to a first surface of the substrate. A second semiconductor die is mounted to a backside of the first semiconductor die. A plurality of connectors electrically connect the first semiconductor die to portions of the conductive traces of the substrate and a plurality of wire bonds connect the second semiconductor die to other portions of the conductive traces of the substrate. An encapsulant encapsulates the wire bonds and covers at least a portion of the first surface of the substrate and the second semiconductor die. A ball grid array is disposed on a second surface of the substrate, bumps of the ball grid array being connected with the conductive traces.Type: GrantFiled: May 7, 2003Date of Patent: November 16, 2004Assignee: ASAT Ltd.Inventor: Serafin P. Pedron, Jr.
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Patent number: 6800948Abstract: An integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink disposed on a portion of the semiconductor die. A plurality of wire bonds connect the semiconductor die to the conductive traces of the substrate and an overmold material covers the first surface of the substrate and a remainder of the semiconductor die. A ball grid array is disposed on the second surface of the substrate. Bumps of the ball grid array are in electrical connection with the conductive traces.Type: GrantFiled: July 19, 2002Date of Patent: October 5, 2004Assignee: ASAT Ltd.Inventors: Chun Ho Fan, Joseph Andrew Martin, Ming Wang Sze, Tak Sang Yeung
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Patent number: 6781242Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. The substrate further has a cavity therein and a heat slug is fixed to the substrate and spans the cavity. A semiconductor die is mounted to the heat slug such that at least a portion of the semiconductor die is disposed in the cavity. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulating material encapsulates the wire bonds and the semiconductor die. A ball grid array is disposed on the first surface of the substrate. Bumps of the ball grid array are in electrical connection with ones of the conductive traces.Type: GrantFiled: December 2, 2002Date of Patent: August 24, 2004Assignee: ASAT, Ltd.Inventors: Chun Ho Fan, Kwok Cheung Tsang, William Lap Keung Chow
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Patent number: 6737755Abstract: An integrated circuit package is provided. The package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween. A semiconductor die is mounted on the first surface of the substrate and an adapter disposed on the semiconductor die. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate, and an encapsulant encapsulates the wirebonds and a remainder of the semiconductor die. A heat spreader has a top portion in contact with the adapter and at least one sidewall extends from the top portion. At least a portion of the at least one sidewall is in contact with the substrate. A ball grid array is disposed on the second surface of the substrate, bumps of the ball grid array being in electrical connection with ones of the conductive traces.Type: GrantFiled: December 19, 2002Date of Patent: May 18, 2004Assignee: Asat, Ltd.Inventors: Neil McLellan, Ming Wang Sze, Wing Keung Lam, Kin-wai Wong
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Patent number: 6734044Abstract: A method of fabricating an integrated circuit package. The method includes providing a first leadframe and a second leadframe, laminating the second leadframe to a portion of the first leadframe in order to create a multi-layer laminated leadframe, and mounting a semiconductor die on another portion of the first leadframe.Type: GrantFiled: June 10, 2002Date of Patent: May 11, 2004Assignee: ASAT Ltd.Inventors: Chun Ho Fan, Tsui Yee Lin, Kin Pui Kwan, Shui Ming Tse, Wing Him Lau, Shuk Man Wong
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Patent number: 6667191Abstract: An integrated circuit package including a silicon wafer, a plate of intermetallic compound fixed to the back surface of the silicon wafer and a plurality of solder ball contacts. The solder ball contacts are in electrical connection with die circuitry on the front surface of the silicon wafer.Type: GrantFiled: August 5, 2002Date of Patent: December 23, 2003Assignee: Asat Ltd.Inventors: Neil McLellan, Wing Him Lau, Tak Sang Yeung, Onofre A. Rulloda, Jr.
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Patent number: 6635957Abstract: A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire bonds connect the semiconductor die, the contact pads and the power/ground ring. An overmold covers the semiconductor die, the die attach pads, the power/ground ring and the contact pads such that each of the die attach pads and the contact pads has one exposed surface.Type: GrantFiled: March 9, 2001Date of Patent: October 21, 2003Assignee: ASAT Ltd.Inventors: Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil Mclellan
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Patent number: 6586834Abstract: An integrated circuit package including a flexible circuit tape having a flexible polyimide tape laminated to a conductor layer, a plurality of blind holes extending through the flexible tape to the conductor layer and a plurality of through holes extending through the flexible tape and the conductor layer. A copper leadframe is fixed to the flexible circuit tape and electrically isolated from the conductor layer. The copper leadframe includes an etched down die attach pad and heat spreader portions. The die attach pad is etched down such that at least a portion of the die attach pad is reduced in thickness. The through holes in the flexible circuit tape extend through to the copper leadframe. A semiconductor die is mounted on the at least a portion of the die attach pad. Wire bonds extend from pads on the semiconductor die to the die attach pad and from other pads on the semiconductor die to the conductor layer, an encapsulating material encapsulates the semiconductor die and the wire bonds.Type: GrantFiled: June 17, 2002Date of Patent: July 1, 2003Assignee: Asat Ltd.Inventors: Ming Wang Sze, Kwok Cheung Tsang, Wing Keung Lam, Kin-wai Wong
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Patent number: 6585905Abstract: A leadless plastic chip carrier comprising a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The row of contact pads have a thickness greater than the thickness of the portion of the die attach pad. A plurality of wire bonds connect the die attach pad and the contact pads. An overmold covers the semiconductor die and all except one surface of the at least one row of contact pads and the die attach pad.Type: GrantFiled: April 3, 2002Date of Patent: July 1, 2003Assignee: ASAT Ltd.Inventors: Chun Ho Fan, Tsui Yee Lin, Kin Yan Tsang, Neil McLellan
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Patent number: 6498099Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip may then be performed by saw singulation or die punching.Type: GrantFiled: April 8, 1999Date of Patent: December 24, 2002Assignee: ASAT Ltd.Inventors: Neil McLellan, Nelson Fan
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Patent number: 6429048Abstract: A method of fabricating an integrated circuit package for ball grid arrays, comprising the steps of: laminating layers of fiberglass prepreg and copper foil to a copper plate in order to create a three-layer laminated carrier; patterning and etching contact pads for input/output and a power/ground ring; applying a solder mask and plating up the contact pads and the ring with a wire bondable metal surface; forming window openings for receiving semiconductor dies; attaching the dies within the windows, wire bonding the dies to the contact pads and the ring, encapsulating the dies, attaching solder balls to the contact pads to create finished packages and singulating the finished packages into individual packages; and attaching the copper plate portion of each of the individual packages to copper plate heat spreader.Type: GrantFiled: December 5, 2000Date of Patent: August 6, 2002Assignee: ASAT Ltd.Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Pik Ling Lau
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Publication number: 20020068378Abstract: A method of fabricating an integrated circuit package for ball grid arrays, comprising the steps of: laminating layers of fiberglass prepreg and copper foil to a copper plate in order to create a three-layer laminated carrier; patterning and etching contact pads for input/output and a power/ground ring; applying a solder mask and plating up the contact pads and the ring with a wire bondable metal surface; forming window openings for receiving semiconductor dies; attaching the dies within the windows, wire bonding the dies to the contact pads and the ring, encapsulating the dies, attaching solder balls to the contact pads to create finished packages and singulating the finished packages into individual packages; and attaching the copper plate portion of each of the individual packages to copper plate heat spreader.Type: ApplicationFiled: December 5, 2000Publication date: June 6, 2002Applicant: ASAT Ltd.Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Pik Ling Lau
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Patent number: 6294100Abstract: A leadless integrated circuit package, comprising an exposed semiconductor die and contact pads embedded in an over mold, and wires interconnecting the semiconductor die and contact pads.Type: GrantFiled: December 3, 1999Date of Patent: September 25, 2001Assignee: Asat LTDInventors: Nelson Fan, Neil McLellan
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Publication number: 20010014538Abstract: A leadless plastic chip carrier has a plurality of die attach pads on which a singulated semi-conductor die is mounted. At least one row of contact pads circumscribes the plurality of die attach pads and a power/ground ring is intermediate the contact pads and the die attach pads. Wire bonds connect the semiconductor die, the contact pads and the power/ground ring. An overmold covers the semiconductor die, the die attach pads, the power/ground ring and the contact pads such that each of the die attach pads and the contact pads has one exposed surface.Type: ApplicationFiled: March 9, 2001Publication date: August 16, 2001Applicant: ASAT Ltd.Inventors: Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan, Neil Mclellan
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Publication number: 20010008305Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.Type: ApplicationFiled: March 9, 2001Publication date: July 19, 2001Applicant: ASAT Ltd.Inventors: Neil McLellan, Chun Ho Fan, Kwok Cheung Tsang, Kin Pui Kwan, Wing Him Lau