Patents Assigned to ASM Japan K.K.
  • Patent number: 7972961
    Abstract: A method of processing semiconductor substrates includes: depositing a film on a substrate in a reaction chamber; evacuating the reaction chamber without purging the reaction chamber; opening a gate valve and replacing the substrate with a next substrate via the transfer chamber wherein the pressure of the transfer chamber is controlled to be higher than that of the reaction chamber before and while the gate valve is opened; repeating the above steps and removing the substrate from the reaction chamber; and purging and evacuating the reaction chamber, and cleaning the reaction chamber with a cleaning gas.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: July 5, 2011
    Assignee: ASM Japan K.K.
    Inventors: Toru Sugiyama, Ryu Nakano
  • Patent number: 7972980
    Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor as a first precursor and a hydrocarbon gas as a second precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film doped with carbon and having Si—N bonds on the substrate.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: July 5, 2011
    Assignee: ASM Japan K.K.
    Inventors: Woo Jin Lee, Akira Shimizu
  • Publication number: 20110159202
    Abstract: A method for sealing pores at a surface of a dielectric layer formed on a substrate, includes: providing a substrate on which a dielectric layer having a porous surface is formed as an outermost layer; placing the substrate in an evacuatable chamber; irradiating the substrate with UV light in an atmosphere of hydrocarbon and/or oxy-hydrocarbon gas; sealing pores at the porous surface of the dielectric layer as a result of the irradiation; and continuously irradiating the substrate with UV light in the atmosphere of hydrocarbon and/or oxy-hydrocarbon gas until a protective film having a desired thickness is formed on the dielectric layer as a result of the irradiation.
    Type: Application
    Filed: November 24, 2010
    Publication date: June 30, 2011
    Applicant: ASM JAPAN K.K.
    Inventors: Kiyohiro Matsushita, Yosuke Kimura, Ippei Yanagisawa
  • Patent number: 7963736
    Abstract: A semiconductor-processing apparatus includes: a wafer handling chamber; a wafer processing chamber; a wafer handling device; a first photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer partially blocks light received by the first photosensor at a ready-to-load position and substantially entirely blocks light received by the first photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction; and a second photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer does not block light received by the second photosensor at the ready-to-load position and partially blocks light received by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: June 21, 2011
    Assignee: ASM Japan K.K.
    Inventors: Masahiro Takizawa, Masaei Suwada, Masayuki Akagawa
  • Patent number: 7955650
    Abstract: A method for reducing a dielectric constant of a cured film, includes: introducing a source gas at a flow rate of A, a porogen gas at a flow rate of B, an oxidizing gas at a flow rate of C, and an inert gas into a reaction space in which a substrate is place; increasing a ratio of B/(A+B) used as a parameter for controlling a dielectric constant of a cured film, by a degree substantially or nearly in proportion to a target decrease of dielectric constant of a cured film; applying RF power to the reaction space, thereby depositing a film on the substrate by plasma CVD; and curing the film to remove the porogen material, thereby forming pores in the cured film.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: June 7, 2011
    Assignee: ASM Japan K.K.
    Inventor: Naoto Tsuji
  • Patent number: 7945345
    Abstract: A semiconductor manufacturing apparatus includes a first program on a controller and a second program on an interface board between the controller and controlled devices. Both of the programs update their own counters and exchange their counter values with each other, serving as bi-directional software watchdog timers (WDT). If a counter value of the first program on the controller sent to the second program on the interface board is determined to be abnormal by the second program, the second program on the interface board sends commands to the controlled devices to terminate output so that the apparatus is navigated to a safe mode. The first program similarly monitors the counter values of the second program for anomalies. This bi-directional software WDT can be implemented as add-on to software programs that already exist in the controller and the interface board, therefore, this implementation does not incur extra cost of hardware of the apparatus.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 17, 2011
    Assignee: ASM Japan K.K.
    Inventors: Masahiro Takizawa, Tsutomu Makino
  • Publication number: 20110086516
    Abstract: A method of forming dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a hydrogen-containing silicon precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the silicon precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 14, 2011
    Applicant: ASM JAPAN K.K.
    Inventors: Woo Jin Lee, Kuo-wei Hong, Akira Shimizu, Deakyun Jeong
  • Patent number: 7919416
    Abstract: A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: April 5, 2011
    Assignee: ASM Japan K.K.
    Inventors: Woo-Jin Lee, Akira Shimizu, Atsuki Fukazawa
  • Patent number: 7899557
    Abstract: For example, by providing MMF software 10, 11 transferring data using a memory-mapped file respectively in a semiconductor manufacturing apparatus 1 and in an input signal analyzing system 8, data transfer load placed on control software 4 and analyzing software 9 is reduced. Additionally, in the MMF software 10, by inserting counter information in the memory-mapped file and by observing the information by the MMF software 11, communication abnormality is detected.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: March 1, 2011
    Assignee: ASM Japan K.K.
    Inventors: Masahiro Takizawa, Kazuyoshi Ishigaya, Kunio Ootani
  • Publication number: 20110014795
    Abstract: A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 20, 2011
    Applicant: ASM JAPAN K.K.
    Inventors: Woo Jin Lee, Kuo-Wei Hong, Akira Shimizu
  • Patent number: 7842622
    Abstract: A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: November 30, 2010
    Assignee: ASM Japan K.K.
    Inventors: Woo-Jin Lee, Atsuki Fukazawa
  • Publication number: 20100291713
    Abstract: A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 18, 2010
    Applicant: ASM JAPAN K.K.
    Inventors: Woo-Jin Lee, Atsuki Fukazawa
  • Patent number: 7833353
    Abstract: A liquid material vaporization apparatus for a semiconductor processing apparatus includes: a vaporization tank; an inner partition wall disposed in the tank for dividing the interior of the tank into a charging compartment and a vaporization compartment which are liquid-communicatable with each other over an upper edge of the inner partition wall. A liquid material charged in the charging compartment overflows over the upper edge of the inner partition wall toward the vaporization compartment to store and vaporize the liquid material in the vaporization compartment.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 16, 2010
    Assignee: ASM Japan K.K.
    Inventors: Kazunori Furukawahara, Hideaki Fukuda
  • Patent number: 7832353
    Abstract: A semiconductor manufacturing apparatus includes a processing unit for processing at least one wafer; a loading/unloading unit for loading/unloading at least wafer; an input/output chamber for taking in a processed wafer from the processing unit and taking out the processed wafer to the loading/unloading unit, and taking in a unprocessed wafer from the loading/unloading unit and taking out the unprocessed wafer to the reaction unit; and a wafer inspection device for inspecting the processed wafer through a light transmittable top portion of the input/output chamber, through which light is transmittable, while the processed wafer is temporarily placed in the input/output chamber.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: November 16, 2010
    Assignee: ASM Japan K.K.
    Inventors: Masahiro Takizawa, Teruhide Nishino
  • Patent number: 7829159
    Abstract: A method of forming an organosilicon oxide film by plasma CVD includes: (i) adjusting a temperature of a susceptor on which a substrate is placed to lower than 300° C.; (ii) introducing at least tetraethylorthosilicate (TEOS) and oxygen into a reactor in which the susceptor is disposed; (iii) applying high-frequency RF power and low-frequency RF power; and (iv) thereby depositing an organosilicon oxide film on the substrate.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: November 9, 2010
    Assignee: ASM Japan K.K.
    Inventor: Ryu Nakano
  • Patent number: 7831315
    Abstract: A method controls an apparatus such as a semiconductor-processing apparatus including a controller and at least one device controlled by the controller, wherein the controller is provided with an interface for communicating with the device, and the interface has an internal clock for measuring time intervals for the communication. The method includes: replacing a system clock of the controller's operating system, which is used for transmitting instructions to the interface, with the internal clock of the interface; transmitting instructions to the interface from the controller using the time intervals measured by the internal clock substituting the system clock; and transmitting the instructions to the device from the interface using the time intervals measured by the internal clock in the interface, thereby controlling the device.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: November 9, 2010
    Assignee: ASM Japan K.K.
    Inventors: Masahiro Takizawa, Kazuyoshi Ishigaya
  • Patent number: 7825040
    Abstract: A method of filling a recess with an insulation film includes: introducing an alkoxysilane or aminosilane precursor containing neither a Si—C bond nor a C—C bond into a reaction chamber where a substrate having an irregular surface including a recess is placed; and depositing a flowable Si-containing insulation film on the irregular surface of the substrate to fill the recess therewith by plasma reaction at ?50° C. to 100° C.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: November 2, 2010
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Hisashi Tazawa, Jeongseok Ha, Shintaro Ueda
  • Publication number: 20100255218
    Abstract: A method of depositing a silicon oxide film on a resist pattern or etched lines formed on a substrate by plasma enhanced atomic layer deposition (PEALD) includes: providing a substrate on which a resist pattern or etched lines are formed in a PEALD reactor; controlling a temperature of a susceptor on which the substrate is placed at less than 50° C. as a deposition temperature; introducing a silicon-containing precursor and an oxygen-supplying reactant to the PEALD reactor and applying RF power therein in a cycle, while the deposition temperature is controlled substantially or nearly at a constant temperature of less than 50° C., thereby depositing a silicon oxide atomic layer on the resist pattern or etched lines; and repeating the cycle multiple times substantially or nearly at the constant temperature to deposit a silicon oxide atomic film on the resist pattern or etched lines.
    Type: Application
    Filed: April 1, 2009
    Publication date: October 7, 2010
    Applicant: ASM Japan K.K.
    Inventors: Takahiro Oka, Akira Shimizu
  • Patent number: 7807566
    Abstract: A method for determining conditions for forming a dielectric SiOCH film, includes: (i) forming a dielectric SiOCH film on a substrate under conditions; (ii) evaluating the conditions using a ratio of Si—CH3 bonding strength to Si—O bonding strength of the film as formed in step (i); (iii) if the ratio is 2.50 % or higher, confirming the conditions, and if the ratio is less than 2.50 %, changing the conditions by changing at least one of the susceptor temperature, the distance between upper and lower electrodes, the RF power, and the curing time; and (iv) repeating steps (i) to (iii) until the ratio is 2.50 % or higher.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: October 5, 2010
    Assignee: ASM Japan K.K.
    Inventors: Naoto Tsuji, Kiyohiro Matsushita, Manabu Kato, Noboru Takamure
  • Patent number: 7799674
    Abstract: A method for forming interconnect wiring, includes: (i) covering a surface of a connection hole penetrating through interconnect dielectric layers formed on a substrate for interconnect wiring, with an underlying alloy layer selected from the group consisting of an alloy film containing ruthenium (Ru) and at least one other metal atom (M), a nitride film thereof, a carbide film thereof, and an nitride-carbide film thereof, and (ii) filling copper or a copper compound in the connection hole covered with the underlying layer.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: September 21, 2010
    Assignee: ASM Japan K.K.
    Inventors: Hiroshi Shinriki, Hiroaki Inoue