Patents Assigned to Aspeed Technology Inc.
  • Patent number: 12250364
    Abstract: A testing device and a testing method for detecting a stitching defect of a panoramic camera are provided. The testing method includes: accessing the panoramic camera to obtain a stitched image, wherein the stitched image includes a chart image corresponding to a chart, wherein the chart includes multiple black stripes and multiple white stripes; generating a defect image marked with the stitching defect according to the chart image; and outputting the defect image.
    Type: Grant
    Filed: January 16, 2022
    Date of Patent: March 11, 2025
    Assignee: ASPEED Technology Inc.
    Inventor: Chieh-Cheng Liao
  • Patent number: 12135673
    Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: November 5, 2024
    Assignee: ASPEED Technology Inc.
    Inventors: Hung Liu, Chih-Chiang Tsao
  • Publication number: 20240362759
    Abstract: An image enhancement method and an electronic device are disclosed. The image enhancement method includes the following steps. An original image is divided into multiple image blocks. A statistical data of each of the image blocks is calculated, and at least one index is obtained according to the statistical data of the each of the image blocks. A final tone mapping curve of the each of the image blocks is obtained based on multiple predefined tone mapping curves according to the at least one index of the each of the image blocks. Afterwards, the original image is adjusted according to the final tone mapping curve of the each of the image blocks to obtain an enhanced image.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 31, 2024
    Applicant: ASPEED Technology Inc.
    Inventor: Hsin-Hui Chen
  • Publication number: 20240345640
    Abstract: Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.
    Type: Application
    Filed: October 5, 2023
    Publication date: October 17, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Shih-Fang Chen, Chin-Ting Kuo, Chia-Wei Wang, Chih-Chiang Mao
  • Patent number: 12119073
    Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: October 15, 2024
    Assignee: ASPEED Technology Inc.
    Inventors: Hung-Ming Lin, Hung-Ju Huang
  • Publication number: 20240323042
    Abstract: An image processing system and an image processing method for a video conferencing software are provided. The image processing method includes: capturing a first original image by a first image capture device and capturing a second original image by a second image capture device; generating first information corresponding to the first original image and transmitting the first information to the first image capture device; cropping a first cropped image from the first original image according to a first mapping relationship in the first information by the first image capture device; and outputting an output image including the first cropped image and a second cropped image corresponding to the second original image to the video conferencing software according to a second mapping relationship in the first information by the first image capture device.
    Type: Application
    Filed: June 27, 2023
    Publication date: September 26, 2024
    Applicant: ASPEED Technology Inc.
    Inventor: Chen-Wei Chou
  • Publication number: 20240320328
    Abstract: An event reporting method, a security management circuit, and a management system are provided. The management system includes first, second, and third security management circuits. The first security management circuit and the second security management are respectively located at a first layer and a second layer of a hierarchy structure. The third security management circuit is located at another layer of the hierarchy structure different from the first layer and the second layer. The first, second, and third security management circuits are respectively configured to determine an event occurring on a host connected to these security management circuits. A dedicated line is communicatively connected between the first and third security management circuits. According to a type of the event determined by the third security management circuit, the third security management circuit reports the event through the dedicated line. Accordingly, a reporting efficiency and system security are improved.
    Type: Application
    Filed: November 24, 2023
    Publication date: September 26, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Chin-Ting Kuo, Chia-Wei Wang, Hung Liu
  • Patent number: 12100163
    Abstract: An object tracking method and an object tracking apparatus, which are adapted for a low latency application, are provided. In the method, an object detection is performed on one of continuous image frames. The objection detection is configured to identify a target. The continuous image frames are temporarily stored. An objection tracking is performed on the temporarily stored continuous image frames according to a result of the object detection. The objection tracking is configured to associate the target in one of the continuous image frames with the target in another of the continuous image frames. Accordingly, the accuracy of object tracking may be improved, and the requirement for low latency may be satisfied.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: September 24, 2024
    Assignee: ASPEED Technology Inc.
    Inventors: Jyun-Kai Syong, Chen-Wei Chou
  • Publication number: 20240232334
    Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.
    Type: Application
    Filed: December 15, 2022
    Publication date: July 11, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Chin-Ting Kuo, Chia-Wei Wang, Hung Liu
  • Publication number: 20240232116
    Abstract: A baseboard management control device is provided. The baseboard management control device includes an input and output device and a baseboard management controller. The input and output device includes a sensing device. The sensing device is coupled to multiple input pins and multiple output pins to sense and write the target data, respectively. The baseboard management controller includes a storage device and a main processor. The storage device is configured to pre-store the target data. The main processor is coupled to the storage device and reads the target data in the storage device according to a predetermined cycle. The baseboard management controller and the input and output device are respectively located on different circuit boards.
    Type: Application
    Filed: May 4, 2023
    Publication date: July 11, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Po-Wei Huang, Chih-Chiang Mao
  • Publication number: 20240232123
    Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.
    Type: Application
    Filed: December 19, 2022
    Publication date: July 11, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Hung Liu, Chih-Chiang Tsao
  • Publication number: 20240202868
    Abstract: An image processing device and an image processing method of generating a layout including a plurality of images are provided. The method includes: partitioning the layout into a plurality of tiles; selecting a first tile located at a border of a first display region and a second display region, and cropping a first sub-block from the first tile; mapping the first sub-block to a calibration map to obtain a mapping region; in response to a third vertex in the mapping region corresponding to a first vertex and a second vertex, performing an interpolation operation on a first data structure and a second data structure to obtain a third data structure corresponding to the third vertex; generating a composed vertex list according to the third vertex and the third data structure; and generating an output image by mapping an input image to the layout according to the composed vertex list.
    Type: Application
    Filed: May 10, 2023
    Publication date: June 20, 2024
    Applicant: ASPEED Technology Inc.
    Inventor: Chia-Wei Hsiao
  • Publication number: 20240134816
    Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 25, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Hung Liu, Chih-Chiang Tsao
  • Publication number: 20240134968
    Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 25, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Chin-Ting Kuo, Chia-Wei Wang, Hung Liu
  • Publication number: 20240126928
    Abstract: A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 18, 2024
    Applicant: ASPEED Technology Inc.
    Inventors: Chin-Ting Kuo, Chih-Chiang Mao
  • Publication number: 20230377676
    Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.
    Type: Application
    Filed: August 9, 2022
    Publication date: November 23, 2023
    Applicant: ASPEED Technology Inc.
    Inventors: Hung-Ming Lin, Hung-Ju Huang
  • Patent number: 11689380
    Abstract: A method and a device for viewing a conference are provided. In the method, after a wide-view video of a specific conference, related conference event data, and speech content of each participant are obtained, a highlight video of the specific conference is correspondingly generated. Accordingly, the efficiency of conference viewing is improved.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: June 27, 2023
    Assignee: ASPEED Technology Inc.
    Inventor: Chen-Wei Chou
  • Patent number: 11664792
    Abstract: An electronic device and data transmission protection device thereof are provided. The data transmission protection device includes an input clock signal detector and a control signal generator. The input clock signal detector receives a reference clock signal, and detects a frequency of an input clock signal provided by a host end according to the reference clock signal, and frequencies of the reference clock signal and the input clock signal are different. The control signal generator enables a generated control signal when the frequency of the input clock signal is larger than a safety setting value. The control signal is used to disable the host end to perform a data accessing operation on a protected circuit.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: May 30, 2023
    Assignee: ASPEED Technology Inc.
    Inventors: Chin-Ting Kuo, Chih-Chiang Mao
  • Publication number: 20230105785
    Abstract: A video content providing method and a video content providing device are provided. The method includes the following. A wide viewing angle image stream and a corresponding first audio content are obtained. A plurality of regions of interest in the wide viewing angle image stream are determined, and candidate regions in the regions of interest are integrated into a first frame. A designated region is selected from the candidate regions, and a corresponding first audio component are found from the first audio content. Each first audio component is suppressed to adjust the first audio content into a second audio content. The first frame and the second audio content are integrated into a specific video content, and the specific video content is provided.
    Type: Application
    Filed: August 22, 2022
    Publication date: April 6, 2023
    Applicant: ASPEED Technology Inc.
    Inventors: Chien-Chou Yang, Chen-Wei Chou
  • Patent number: 11615048
    Abstract: An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 28, 2023
    Assignee: ASPEED Technology Inc.
    Inventors: Hung-Ming Lin, Chih-Chiang Mao