Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.

Abstract: An image enhancement method and an electronic device are disclosed. The image enhancement method includes the following steps. An original image is divided into multiple image blocks. A statistical data of each of the image blocks is calculated, and at least one index is obtained according to the statistical data of the each of the image blocks. A final tone mapping curve of the each of the image blocks is obtained based on multiple predefined tone mapping curves according to the at least one index of the each of the image blocks. Afterwards, the original image is adjusted according to the final tone mapping curve of the each of the image blocks to obtain an enhanced image.

Abstract: Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.

Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

Abstract: An event reporting method, a security management circuit, and a management system are provided. The management system includes first, second, and third security management circuits. The first security management circuit and the second security management are respectively located at a first layer and a second layer of a hierarchy structure. The third security management circuit is located at another layer of the hierarchy structure different from the first layer and the second layer. The first, second, and third security management circuits are respectively configured to determine an event occurring on a host connected to these security management circuits. A dedicated line is communicatively connected between the first and third security management circuits. According to a type of the event determined by the third security management circuit, the third security management circuit reports the event through the dedicated line. Accordingly, a reporting efficiency and system security are improved.

Abstract: An image processing system and an image processing method for a video conferencing software are provided. The image processing method includes: capturing a first original image by a first image capture device and capturing a second original image by a second image capture device; generating first information corresponding to the first original image and transmitting the first information to the first image capture device; cropping a first cropped image from the first original image according to a first mapping relationship in the first information by the first image capture device; and outputting an output image including the first cropped image and a second cropped image corresponding to the second original image to the video conferencing software according to a second mapping relationship in the first information by the first image capture device.

Abstract: An object tracking method and an object tracking apparatus, which are adapted for a low latency application, are provided. In the method, an object detection is performed on one of continuous image frames. The objection detection is configured to identify a target. The continuous image frames are temporarily stored. An objection tracking is performed on the temporarily stored continuous image frames according to a result of the object detection. The objection tracking is configured to associate the target in one of the continuous image frames with the target in another of the continuous image frames. Accordingly, the accuracy of object tracking may be improved, and the requirement for low latency may be satisfied.

Abstract: An image processing system is disclosed, comprising a multiple-lens camera, a vertex list generator and an image processing apparatus. The multiple-lens camera captures a X-degree horizontal field of view (FOV) and a Y-degree vertical FOV to generate multiple lens images, where X<=360, Y<=180. The vertex list generator generates a first main vertex list according to a correspondence table, and generates a first region of interest (ROI) vertex list according to the first main vertex list and a position information of the ROI when the ROI overlaps at least one measuring region inside an overlap region in a projection image. The image processing apparatus generates the projection image according to the multiple lens images and a second main vertex list related to first main vertex list in a rendering mode.

Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.

Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.

Abstract: A baseboard management control device is provided. The baseboard management control device includes an input and output device and a baseboard management controller. The input and output device includes a sensing device. The sensing device is coupled to multiple input pins and multiple output pins to sense and write the target data, respectively. The baseboard management controller includes a storage device and a main processor. The storage device is configured to pre-store the target data. The main processor is coupled to the storage device and reads the target data in the storage device according to a predetermined cycle. The baseboard management controller and the input and output device are respectively located on different circuit boards.

Abstract: An image processing device and an image processing method of generating a layout including a plurality of images are provided. The method includes: partitioning the layout into a plurality of tiles; selecting a first tile located at a border of a first display region and a second display region, and cropping a first sub-block from the first tile; mapping the first sub-block to a calibration map to obtain a mapping region; in response to a third vertex in the mapping region corresponding to a first vertex and a second vertex, performing an interpolation operation on a first data structure and a second data structure to obtain a third data structure corresponding to the third vertex; generating a composed vertex list according to the third vertex and the third data structure; and generating an output image by mapping an input image to the layout according to the composed vertex list.

Abstract: A baseboard management controller (BMC) and an operation method thereof are provided. The BMC includes a path switching circuit, a host interface circuit, a universal serial bus (USB) hub controller, a USB physical layer circuit, and a control circuit. The host interface circuit is adapted to be electrically connected to a host circuit outside the BMC. The USB physical layer circuit is adapted to be electrically connected to an external USB host or an external USB device outside the BMC. The control circuit controls the path switching circuit to selectively couple the host interface circuit to the USB hub controller, selectively couple the USB hub controller to the USB physical layer circuit, or selectively couple the host interface circuit to the USB physical layer circuit.

Abstract: An electronic system and a security authority delegation method thereof are provided. The electronic system includes a first host device, a second host device, a first security device, and a second security device. The first security device is connected to the first host device. The second security device is connected to the second host device and the first security device. The first security device performs an attestation process on the second security device. If the second security device passes the attestation process, the first security device enables the second security device to verify executable images of the second host device. If the second security device does not pass the attestation process, the first security device disables a function of the second security device, and the function includes verifying the executable image of the second host device.

Abstract: A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.

Abstract: An image processing method for receiving M lens images and generating a projection image is disclosed. The method comprises: determining P optimal warping coefficients of P control regions in the projection image according to a 2D error table and the M lens images from an image capture module; generating M projection images according to the M lens images, a first vertex list and the P optimal warping coefficients; determining a seam for each of N seam regions; and, stitching two overlapping seam images to generate a stitched seam image for each seam region according to its corresponding seam. The 2D error table comprises multiple test warping coefficients and multiple accumulation pixel value differences in the P control regions. The P control regions are respectively located in the N seam regions respectively located in N overlap regions, where M>=2, N>=1 and P>=3.

Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

Abstract: A multiple-processor system for a multiple-lens camera is disclosed. The system comprises multiple processor components (PCs) and multiple links. Each PC comprises multiple I/O ports and a processing unit. The multiple-lens camera captures a X-degree horizontal field of view and a Y-degree vertical field of view, where X<=360 and Y<180. Each link conjects one of the I/O ports of one of the PCs to one of the I/O ports of another one of the PCs such that each PC is conjected by two or more respective links to one or two neighboring PCs. Each link is configured to transfer data in one direction.

Abstract: A method and a device for viewing a conference are provided. In the method, after a wide-view video of a specific conference, related conference event data, and speech content of each participant are obtained, a highlight video of the specific conference is correspondingly generated. Accordingly, the efficiency of conference viewing is improved.

Abstract: A polyhedron lens architecture is disposed in a virtual sphere. The virtual sphere has a horizontal plane, an upper hemisphere above the horizontal plane and a lower hemisphere below the horizontal plane. The polyhedron lens architecture has an upper half part above the horizontal plane, and a lower half part below the horizontal plane. The polyhedron lens architecture includes: multiple bases, which are respectively disposed on the upper half part and the lower half part; and multiple lenses respectively disposed on surfaces of the bases. Optical axes of the lenses intersect at a central point, which is located at the horizontal plane and is a structural center of the polyhedron lens architecture.