Patents Assigned to Aspeed Technology Inc.
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Publication number: 20230377676Abstract: The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.Type: ApplicationFiled: August 9, 2022Publication date: November 23, 2023Applicant: ASPEED Technology Inc.Inventors: Hung-Ming Lin, Hung-Ju Huang
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Patent number: 11689380Abstract: A method and a device for viewing a conference are provided. In the method, after a wide-view video of a specific conference, related conference event data, and speech content of each participant are obtained, a highlight video of the specific conference is correspondingly generated. Accordingly, the efficiency of conference viewing is improved.Type: GrantFiled: November 23, 2021Date of Patent: June 27, 2023Assignee: ASPEED Technology Inc.Inventor: Chen-Wei Chou
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Patent number: 11664792Abstract: An electronic device and data transmission protection device thereof are provided. The data transmission protection device includes an input clock signal detector and a control signal generator. The input clock signal detector receives a reference clock signal, and detects a frequency of an input clock signal provided by a host end according to the reference clock signal, and frequencies of the reference clock signal and the input clock signal are different. The control signal generator enables a generated control signal when the frequency of the input clock signal is larger than a safety setting value. The control signal is used to disable the host end to perform a data accessing operation on a protected circuit.Type: GrantFiled: June 2, 2022Date of Patent: May 30, 2023Assignee: ASPEED Technology Inc.Inventors: Chin-Ting Kuo, Chih-Chiang Mao
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Publication number: 20230105785Abstract: A video content providing method and a video content providing device are provided. The method includes the following. A wide viewing angle image stream and a corresponding first audio content are obtained. A plurality of regions of interest in the wide viewing angle image stream are determined, and candidate regions in the regions of interest are integrated into a first frame. A designated region is selected from the candidate regions, and a corresponding first audio component are found from the first audio content. Each first audio component is suppressed to adjust the first audio content into a second audio content. The first frame and the second audio content are integrated into a specific video content, and the specific video content is provided.Type: ApplicationFiled: August 22, 2022Publication date: April 6, 2023Applicant: ASPEED Technology Inc.Inventors: Chien-Chou Yang, Chen-Wei Chou
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Patent number: 11615048Abstract: An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.Type: GrantFiled: December 6, 2021Date of Patent: March 28, 2023Assignee: ASPEED Technology Inc.Inventors: Hung-Ming Lin, Chih-Chiang Mao
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Publication number: 20230022221Abstract: An object tracking method and an object tracking apparatus, which are adapted for a low latency application, are provided. In the method, an object detection is performed on one of continuous image frames. The objection detection is configured to identify a target. The continuous image frames are temporarily stored. An objection tracking is performed on the temporarily stored continuous image frames according to a result of the object detection. The objection tracking is configured to associate the target in one of the continuous image frames with the target in another of the continuous image frames. Accordingly, the accuracy of object tracking may be improved, and the requirement for low latency may be satisfied.Type: ApplicationFiled: August 26, 2021Publication date: January 26, 2023Applicant: ASPEED Technology Inc.Inventors: Jyun-Kai Syong, Chen-Wei Chou
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Publication number: 20230006851Abstract: A method and a device for viewing a conference are provided. In the method, after a wide-view video of a specific conference, related conference event data, and speech content of each participant are obtained, a highlight video of the specific conference is correspondingly generated. Accordingly, the efficiency of conference viewing is improved.Type: ApplicationFiled: November 23, 2021Publication date: January 5, 2023Applicant: ASPEED Technology Inc.Inventor: Chen-Wei Chou
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Patent number: 11502712Abstract: A signal transceiving system and a signal receiver thereof are provided. The signal transceiving system includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. The comparator compares, in a first mode, the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder generates, in the first mode, at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value which is a serial signal and the instruction signal to a signal receiver.Type: GrantFiled: April 13, 2021Date of Patent: November 15, 2022Assignee: ASPEED Technology Inc.Inventors: Hung-Ming Lin, Chih-Chiang Mao
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Publication number: 20220283979Abstract: An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.Type: ApplicationFiled: December 6, 2021Publication date: September 8, 2022Applicant: ASPEED Technology Inc.Inventors: Hung-Ming Lin, Chih-Chiang Mao
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Publication number: 20220286155Abstract: A signal transceiving system and a signal receiver thereof are provided. The signal transceiving system includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. The comparator compares, in a first mode, the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder generates, in the first mode, at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value which is a serial signal and the instruction signal to a signal receiver.Type: ApplicationFiled: April 13, 2021Publication date: September 8, 2022Applicant: ASPEED Technology Inc.Inventors: Hung-Ming Lin, Chih-Chiang Mao
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Patent number: 11210840Abstract: A transform method applied in an image processing system is disclosed, comprising: when the image capture module is rotated, respectively performing inverse rotation operations over post-rotation space coordinates of three first vertices from a integral vertex stream according to rotation angles of the image capture module to obtain their pre-rotation space coordinates; calculating pre-rotation longitudes and latitudes of the three first vertices according to their pre-rotation space coordinates; selecting one from a pre-rotation panoramic image, a south polar image and a north polar image as a texture image to determine a texture ID for the three first vertices according to their pre-rotation latitudes; and, calculating pre-rotation texture coordinates according to the texture ID and the pre-rotation longitudes and latitudes to form a first complete data structure for each of the three first vertices.Type: GrantFiled: August 27, 2020Date of Patent: December 28, 2021Assignee: Aspeed Technology Inc.Inventor: Chung-Yen Lu
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Patent number: 10013369Abstract: A server system is disclosed. The server system comprises a host system, at least one hard disk (HD) drive, a host bus adapter (HBA), at least one indicator, a storage enclosure processor (SEP), a baseboard management controller (BMC) and a snoop device. The HBA is used to issue a bus signal in a format suitable for transmission over a serial bus according to the received drive state from the at least one HD drive and send the bus signal over the serial bus. The SEP receives the bus signal over the serial bus and drives the at least one indicator to corresponding states. The BMC is coupled to a network. The snoop device detects the bus signal over the serial bus and sends a warning signal to the BMC when a drive failure event is detected.Type: GrantFiled: October 30, 2015Date of Patent: July 3, 2018Assignee: Aspeed Technology Inc.Inventor: Chien-Chou Chen
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Patent number: 9857865Abstract: A power measurement circuit is disclosed. The power measurement circuit comprises a sampling register, a latch generator, an accumulation unit, a calculation unit and an output register. The sampling register samples an input signal based on a sampling clock to generate a binary digit. The latch generator generates a latch signal based on the sampling clock and a measurement interval. The accumulation unit accumulates the binary digit based on the latch signal to generate a sum value. The calculation unit calculates an ON-phase rate of the input signal according to the sum value and the measurement interval. The output register stores a power consumption value according to the ON-phase rate of the input signal.Type: GrantFiled: December 10, 2015Date of Patent: January 2, 2018Assignee: Aspeed Technology Inc.Inventors: Chung-Yen Lu, Hung-Ming Lin
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Publication number: 20150234750Abstract: A method of accessing a desired memory location applied in a cipher processing apparatus is disclosed. The cipher processing apparatus comprises a plurality of registers and a register storage. The method comprises the steps of: reading a cipher instruction comprising an opcode field and an operand specifier field; reading a base address from one of the plurality of registers according to a register-id sub-field; respectively reading a bit length and an index value from the register storage and an index sub-field; determining the desired memory location according to the base address, the bit length and the index value; and, accessing the desired memory location to obtain a desired field variable. Here, the operand specifier field comprises the register-id sub-field and the index sub-field.Type: ApplicationFiled: February 18, 2014Publication date: August 20, 2015Applicant: ASPEED Technology Inc.Inventors: Chung-Yen LU, Hung-Ju HUANG
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Publication number: 20150189393Abstract: An image transmission system with finite re-transmission function is disclosed. The system of the invention comprises a communication channel, a transmitting device and a receiving device. The transmitting device comprises an encoder, a first coded buffer and a transmitter. The receiving device comprises a receiver, a second coded buffer, a decoder, a decoded buffer and a display control unit. The system of the invention uses line buffers due to its line-based encoding/decoding scheme, to thereby reduce hardware cost. In addition, the image transmission system of the invention conducts a skip-line-encoding mechanism, a stop-retransmitting mechanism and a line-ID-control mechanism, to thereby achieve a real-time transmission/display.Type: ApplicationFiled: January 2, 2014Publication date: July 2, 2015Applicant: ASPEED Technology Inc.Inventor: Chung-Yen LU
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Publication number: 20150156517Abstract: An image encoding system is disclosed. The image encoding system comprises a wavelet transform unit and a processing circuit. The wavelet transform unit performs a multiple-line-based wavelet transform on plural consecutive component lines to generate a wavelet transformed image comprising wavelet coefficients of plural sub-bands. The processing circuit coupled to the wavelet transform unit for quantizing, scanning and encoding the wavelet coefficients to generate a compressed image. Here, a number of the plural consecutive component lines is a multiple of 2 and less than 5. Since the wavelet transform unit performs the multiple-line-based wavelet transform to reduce the storage amount and maintain a good compression quality, an image encoding system of the invention can use SRAM buffers instead of a DRAM buffer.Type: ApplicationFiled: December 4, 2013Publication date: June 4, 2015Applicant: ASPEED Technology Inc.Inventor: Chung-Yen LU
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Publication number: 20140344431Abstract: A baseboard management system suitable for use in a high density server system is provided. The baseboard management system comprises: a plurality of baseboard management controller (BMC) node respectively located on the servers; and, a main BMC coupled to a network and to the BMC nodes through a communication link for executing a management software; wherein each BMC node is connected with a corresponding host processor and with server board peripherals individually on a corresponding server; and wherein the main BMC in cooperation with the BMC nodes is used to manage the servers remotely.Type: ApplicationFiled: May 16, 2013Publication date: November 20, 2014Applicant: ASPEED Technology Inc.Inventors: FU-CHOU HSU, HUNG-JU HUANG, Chung-Yen LU
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Patent number: 8698531Abstract: An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.Type: GrantFiled: February 5, 2013Date of Patent: April 15, 2014Assignee: Aspeed Technology, Inc.Inventors: Fu-Chou Hsu, Hung-Ju Huang, Chung-Yen Lu
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Patent number: 8700807Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.Type: GrantFiled: June 28, 2012Date of Patent: April 15, 2014Assignee: ASPEED Technology Inc.Inventors: Hung-Ju Huang, Shu-An Huang Ho, Jen-Min Yuan
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Patent number: 8422573Abstract: The invention discloses a transmitting apparatus. The transmitting apparatus uses the same transmission medium to transmit two signals that are within different frequency ranges at the same time. The transmitting apparatus increases the transmitting paths of the transmission medium so as to enhance the use of the transmission medium and save the production costs.Type: GrantFiled: July 16, 2009Date of Patent: April 16, 2013Assignee: ASPEED Technology Inc.Inventors: Hung-Ming Lin, Hung-Ju Huang, Fu-Chou Hsu