Abstract: An electronic keyboard template for use with software applications programs is responsive to command signals transmitted by designated function keys on a computer keyboard. The template includes an LCD display screen for displaying icons representative of operations performed by the function keys, control circuitry, and driving circuitry for generating the display of the icons on the LCD screen. In a preferred embodiment, the control circuitry includes a microprocesor, a Random-Access-Memory, and a digital Look-Up-Table, and the driving circuitry comprises a matrix driver and a refresh sequencer. The driving circuitry may further include a DC-to-DC convertor, and a plurality of shift registers for energizing pixel locations designated within a grid system on the LCD screen. In an alternative embodiment, the control circuitry may be external to the template (e.g., within the keyboard).

Abstract: A system for integrating incompatible hard disk partitioning systems in a single hard disk drive provides a method for installing and operating multiple incompatible absolute zero sector operating systems on the same hard disk drive with a first operating system and its associated boot loader located at absolute physical sector zero and a second operating system and its associated boot loader located at an absolute physical sector other than zero. The system includes a second BIOS that automatically offsets physical addresses for disk requests from the second operating system so that correct absolute physical address of the disk is accessed. This facilitates the use of a single hard disk drive in dual-compatible computers which functions selectively in an IBM AT compatible mode and a non-IBM AT compatible mode.

Abstract: A system for controlling daisy-chain testing of removable printed circuit boards installed along a backplane bus facilitates the use of serial testing methods for circuit boards which are designed according to boundary-scan testing standards. The system automatically controls propagation of serial test data from a serial data pattern generator to a removable circuit board and then from circuit board to circuit board as installed consecutively along the backplane bus, and from the last circuit board installed on the bus to a pattern comparator which determines whether the pattern matches an expected pattern to isolate components on the circuit boards which are not functioning properly.

Abstract: A system for selectively controlling individual expansion slots in an IBM-AT/NEC 9801 dual compatible computer provides automatic control for the individual ISA bus expansion slots in the computer. This facilitates the use of an Industry Standard Architecture (ISA) bus and ISA (AT) type add-on cards in the dual compatible computer. A user configures each slot as containing either a card which may interfere with operations of the computer in the non-IBM-AT compatible mode or a card which will not interfere with computer operations in the non-IBM-AT compatible mode. Thereafter, the computer automatically disables the cards in accordance with the mode of computer operation.

Abstract: An asynchronous circuit utilizes toggle flip-flops to receive a plurality of asynchronous input signals. The input signals are applied to the edge-triggered clock inputs of the toggle flip-flops so that outputs of the toggle flip-flops and other logic signals within the asynchronous circuit change with respect to particular edges of the input signals. An output signal is responsive to the changes in the outputs of the toggle flip-flops and is thus responsive to the changes in the asynchronous input signals. Since the input signals have well-defined transitions which cause the changes in the output signals, various parameters, such as propagation delays, can be measured and characterized. The asynchronous logic circuit thus provides the operational advantages of asynchronous circuits while exhibiting the testability characteristics of clocked logic circuits.

Abstract: A compact system unit for personal computers wherein system hardware components are closely integrated and packed resulting in an effective utilization of space. Such compact integration of hardware is facilitated by the arrangement of system hardware components co-planar with each other. The compact system unit incorporates a hard disk and a floppy disk. The floppy disk controller card is co-planar with and plugs directly on to the mother board. A bus expansion card is vertically mounted to the mother board whereby up to two additional optional expansion cards may be incorporated in a parallel formation within the compact system unit. The daughter board is directly mounted to the mother board in inverted orientation.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: A circuit for synchronizing an asynchronous input signal with an internal time base clock operates at a high frequency. The circuit includes an input flip-flop that receives the input signal and an output flip-flop that provides an output signal that is synchronized with the internal time base clock. The input flip-flop and the output flip-flop are interconnected via logic circuitry so that any instability on the output of the input flip-flop caused by failure of the input signal to satisfy the setup and hold conditions of the input flip-flop are isolated from the output of the output flip-flop. The output of the output flip-flop is a stable signal that is synchronized with the internal time base clock.

Abstract: A multi-layer printed circuit board is constructed to suppress radio frequency interference (RFI) generated by high frequency clock and data signals therein. Suppression is achieved by positioning clock lines carrying the clock signal on a first voltage reference layer proximate to a second voltage reference layer. The two layers shield the clock signal from the signal lines on other layers. Noise may be further reduced by forming bridges in the second voltage reference layer proximate to the clock lines so that the bridges span the width of the clock line. Capacitors are also preferably utilized to further suppress radiated noise. The capacitors provide AC coupling between the first and second voltage reference layers so that a low impedance path is provided for high frequency noise generated by the clock signal. The second voltage reference layer thus operates as an effectively continuous shield between the bridges.