Abstract: A memory mapped keyboard controller within a peripheral controller for use in an Industry Standard Architecture (ISA) computer provides a method and apparatus for efficiently monitoring and reading a keyboard switch matrix. In a first mode of operation, the controller activates all the columns and monitors all the rows in the switch matrix to detect when any one or more of the rows becomes active, indicating that at least one key on the keyboard has been pressed. When any row in the matrix is detected as active, then the keyboard controller enters a second mode wherein it selectively activates individual columns and monitors the rows in the switch matrix to detect which row and column contain the activated switch. When the switch location is determined, this location is interpreted by the keyboard controller into a scan code for the ISA computer.

Abstract: A computer pedestal for stably supporting a computer component in an upright orientation can be nestably engaged with other like pedestals to permit side-by-side stowage of a plurality of computer components. The pedestal has a flat parallelepiped-shaped base, and at least one stabilizer extends outwardly from the base to provide lateral support to the base. Also, a channel is formed in the base opposite the stabilizer. The stabilizer is configured to closely conform to the channel, so that the stabilizer can nestably mate with the channel of another like pedestal when the two pedestals are positioned side-by-side. The components that are supported by the nested pedestals can accordingly be closely and stably disposed side-by-side.

Abstract: A method and apparatus for downloading instructions and other information to a peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system which downloads instructions from the ISA compatible computer to an random access memory (RAM) accessible by the peripheral controller. The peripheral controller then executes these instructions to emulate the functions of conventional INTEL 8042 and 8742 series integrated circuits. The peripheral controller also provides other features not provided by the conventional 8042 or 8742 by executing other downloaded instructions located in the RAM.

Abstract: A memory system for use with a copy back cache system includes a control circuit that reduces the amount of time to complete a copy back/line fill operation in which a first line of data from the cache is stored in the memory system and then a second line of data is retrieved from the memory system and transferred to the cache system. Unlike conventional memory systems where the line of data to be copied back is likely to be stored in the memory system at a row address that differs from the row address of the line of data to be retrieved from the memory system for the line fill, the memory system of the present invention assures that the copy back data and the line fill data are located at the same row address in the memory system. Thus, a single row address can be applied once at the beginning of the copy back/line fill operation, thereby saving the row address precharge time and the row address access time required to switch row addresses between the two portions of the operation.

Abstract: A computer system includes an Intel 80486 microprocessor having an internal cache memory and a local memory tightly coupled to the microprocessor that can respond to memory accesses without requiring the microprocessor to execute a wait state. An external cache memory system is provided to provide additional cache storage to provide copy back capabilities so that data written to the external cache does not have to be automatically written to slower bulk memory. The computer system includes a conventional Industry Standard Architecture bus (ISA-bus) which may include memory on the bus. The computer system may also include an external math coprocessor. In order to preclude storing data from the math coprocessor and from the ISA-bus memory, the external cache memory system includes a cache determination circuit that selectively generates a cache enable signal to the microprocessor and to the external cache memory system so that only cacheable data is stored in the two caches.

Abstract: An interrupt driven peripheral controller for use in an Industry Standard Architecture (ISA) compatible computer provides a system to minimize power consumption as compared to conventional peripheral controllers. The peripheral controller utilizes an internal interrupt controller which responds to inputs from an ISA compatible microprocessor host, a keyboard, a mouse, and other devices connected to the I/O ports of the ISA compatible computer. The interrupt controller provides an interrupt register for the peripheral controller and generates an interrupt any time one or more of the devices controlled by the peripheral controller is activated. The peripheral controller enters a low power consumption mode if no interrupts are detected for a predetermined period of time. When the interrupt controller generates an interrupt, the peripheral controller is activated from it low power mode and services the device or devices which have caused the interrupt.

Abstract: A battery monitor system is disclosed comprising a microcontroller which monitors voltage inputs from a power adapter and a rechargeable battery. The power adapter includes a voltage source and a current source which outputs two current levels. A thermistor is thermally coupled to the battery, and the microcontroller receives voltage inputs from the battery and the thermistor. The microcontroller monitors and processes the voltage inputs to detect a predetermined voltage change corresponding to a change in the battery temperature and/or voltage level which indicates a fully charged battery. The level of the current which is provided to the battery from the current source is under the control of the microcontroller, such that the battery is maintained in a fully charged state.

Abstract: An electronic keyboard template for use with software applications programs is responsive to command signals transmitted by designated function keys on a computer keyboard. The template includes an LCD display screen for displaying icons representative of operations performed by the function keys, control circuitry, and driving circuitry for generating the display of the icons on the LCD screen. In a preferred embodiment, the control circuitry includes a microprocesor, a Random-Access-Memory, and a digital Look-Up-Table, and the driving circuitry comprises a matrix driver and a refresh sequencer. The driving circuitry may further include a DC-to-DC convertor, and a plurality of shift registers for energizing pixel locations designated within a grid system on the LCD screen. In an alternative embodiment, the control circuitry may be external to the template (e.g., within the keyboard).

Abstract: A system for controlling daisy-chain testing of removable printed circuit boards installed along a backplane bus facilitates the use of serial testing methods for circuit boards which are designed according to boundary-scan testing standards. The system automatically controls propagation of serial test data from a serial data pattern generator to a removable circuit board and then from circuit board to circuit board as installed consecutively along the backplane bus, and from the last circuit board installed on the bus to a pattern comparator which determines whether the pattern matches an expected pattern to isolate components on the circuit boards which are not functioning properly.

Abstract: A system for selectively controlling individual expansion slots in an IBM-AT/NEC 9801 dual compatible computer provides automatic control for the individual ISA bus expansion slots in the computer. This facilitates the use of an Industry Standard Architecture (ISA) bus and ISA (AT) type add-on cards in the dual compatible computer. A user configures each slot as containing either a card which may interfere with operations of the computer in the non-IBM-AT compatible mode or a card which will not interfere with computer operations in the non-IBM-AT compatible mode. Thereafter, the computer automatically disables the cards in accordance with the mode of computer operation.

Abstract: An asynchronous circuit utilizes toggle flip-flops to receive a plurality of asynchronous input signals. The input signals are applied to the edge-triggered clock inputs of the toggle flip-flops so that outputs of the toggle flip-flops and other logic signals within the asynchronous circuit change with respect to particular edges of the input signals. An output signal is responsive to the changes in the outputs of the toggle flip-flops and is thus responsive to the changes in the asynchronous input signals. Since the input signals have well-defined transitions which cause the changes in the output signals, various parameters, such as propagation delays, can be measured and characterized. The asynchronous logic circuit thus provides the operational advantages of asynchronous circuits while exhibiting the testability characteristics of clocked logic circuits.