Abstract: A compact system unit for personal computers wherein system hardware components are closely integrated and packed resulting in an effective utilization of space. Such compact integration of hardware is facilitated by the arrangement of system hardware components co-planar with each other. The compact system unit incorporates a hard disk and a floppy disk. The floppy disk controller card is co-planar with and plugs directly on to the mother board. A bus expansion card is vertically mounted to the mother board whereby up to two additional optional expansion cards may be incorporated in a parallel formation within the compact system unit. The daughter board is directly mounted to the mother board in inverted orientation.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: A circuit for synchronizing an asynchronous input signal with an internal time base clock operates at a high frequency. The circuit includes an input flip-flop that receives the input signal and an output flip-flop that provides an output signal that is synchronized with the internal time base clock. The input flip-flop and the output flip-flop are interconnected via logic circuitry so that any instability on the output of the input flip-flop caused by failure of the input signal to satisfy the setup and hold conditions of the input flip-flop are isolated from the output of the output flip-flop. The output of the output flip-flop is a stable signal that is synchronized with the internal time base clock.

Abstract: A multi-layer printed circuit board is constructed to suppress radio frequency interference (RFI) generated by high frequency clock and data signals therein. Suppression is achieved by positioning clock lines carrying the clock signal on a first voltage reference layer proximate to a second voltage reference layer. The two layers shield the clock signal from the signal lines on other layers. Noise may be further reduced by forming bridges in the second voltage reference layer proximate to the clock lines so that the bridges span the width of the clock line. Capacitors are also preferably utilized to further suppress radiated noise. The capacitors provide AC coupling between the first and second voltage reference layers so that a low impedance path is provided for high frequency noise generated by the clock signal. The second voltage reference layer thus operates as an effectively continuous shield between the bridges.