Abstract: A method and apparatus for approximating power dissipation using a computer-assisted engineering (CAE) system. Initially, a determination is made of the capacitive load for each cell in a netlist for the CMOS circuit, preferably from cell library data sheets. In addition, the capacitive loads of the interconnects between stages are estimated. A switching rate for each cell is then calculated using one of two alternative methods. The first method assumes that the patterns of input signals are statistically independent, and thus estimates the switching rate from the structure of the cell and the switching rates of the inputs. The second method uses known information concerning the relative times when the input signals are high or low to determine the switching rate of the cell. Once the switching rate is known, the output frequency for the cell can be determined. The power dissipation for each cell is then calculated by multiplying the output frequency by the capacitive load.

Abstract: A solid-state array scanner with a color filter at each pixel sensor is provided to accomplish color scanning of color images with a set of pixels sensors for each color pixel. In addition, a scaler device is provided for selectively scaling the output pixel signal from each pixel sensor to correct for color filter loss when scanning black/white images. Thus, while a set of pixel signals must be combined for each color pixel in color mode scanning, in mono mode scanning of black/white images, the pixel signal from each pixel signal may be used. An address means selectively addresses each solid-state pixel sensor device in the array for readout of the illumination intensity, or pixel signal, sensed by that device. Each pixel sensor will have a given color filter dependent upon the sensor's location in the array. From the address of the pixel sensor, the scaler value to compensate for the color filter in mono mode can be selected.

Abstract: An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.

Abstract: A voltage controlled current source including feedback circuitry which eliminates the need for a current sensing resistor in series with the output voltage controlled current source. The feedback circuit includes circuitry for generating a reference current which is proportional to, but much smaller than, the output current produced by the current source, and current mirror circuitry for generating a sense current which is equivalent to the reference current. The sense current is provided to a current sense resistor, across which a feedback voltage is developed. The voltage controlled current source further includes an amplifier connected to receive an input control voltage and the feedback voltage for generating the output current in response to the input control voltage and the feedback voltage.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A circuit and method for determining the operating performance of an integrated circuit which may be used to screen integrated circuits prior to sale or delivery, or to optimize the frequency of the integrated circuit during use. The circuit employs a comparison circuit to compare a first time of arrival of a clock pulse, which is propagating through the integrated circuit with a second time of arrival of the clock signal at a second input. The comparison circuit produces an output signal which may be used to reject or accept the integrated circuit, or to automatically adjust the frequency to minimize the delay.

Abstract: In a method of, and apparatus for, reading a barcode, a barcode symbol is optically scanned into a memory (13), and a plurality of scans across the stored image are made and processed to determine the barcode. The scans are made at interleaved positions across the barcode, and are stored in a storage device (87) and tested in a testing unit (88) for a consensus of at least 2 scans, further scans being made if necessary. Preferably, more than half the scans should be in matching agreement to determine that a consensus has been reached. Each scan may be averaged from several sub-scans. The scans may be decoded into symbols. Various validity tests may be made on the scans. The scans are analysed by measuring the positions of the black-to-white and white-to-black transitions in them; the positions of the transitions may be interpolated between pixel positions.

Abstract: A mechanical component peripheral lead protector covers fine pitch component leads in such a manner that nothing can come into contact with them. The lead protector is disposed above the component having the leads. It can be made of aluminum, conductive plastic or any other non ESD (electric static discharge) generating material. It can be glued, snapped, bolted or riveted to the associated PC board or glued to the top of the component, depending upon the application in which it is being used. The attachment method should be one which enables it to be removed and replaced when necessary. The center of the lead protector can be provided with an aperture so that the legends on the top of the component will be exposed.

Abstract: A method and apparatus for very low, in some case even zero, data latency accesses to a shared resource for devices such as disk drives and their channel formatting agents. The method and apparatus together will controllably terminate any non-low-latency access in process and then start a low latency access. Since the computer system has a group of three agents that may require low latency accesses, a special low latency arbitration method and apparatus is provided instead of the normal dynamic time loop arbitration. The low latency arbitration is call zero latency loop arbitration. The method and apparatus can actually provide zero latency data accesses for disk reads and writes in many cases. Once all low latency accesses are fulfilled, the method and apparatus allow the computer system to return to its slower, normal dynamic timed loop arbitration.

Abstract: A Peripheral Component Interconnect (PCI) bus provides component level interconnection of processors, peripherals and memories. A bus protocol mechanism includes a Special Cycle command for defining "soft", i.e., configurable, transaction types for use between devices communicating on the PCI bus. Using the Special Cycle command, two or more devices attached to the bus can establish a device-specific logical signalling channel that expands upon, but does not violate, the PCI specification. This device-specific signalling channel provides logical sideband signaling between PCI bus devices, when such signaling does not require the precise timing or synchronization of physical signals. This allows the systems designer to define necessary sideband signalling without requiring any additional pins on the PCI bus.

Abstract: A three dimensional logic cube comprises a base plate having two vertically mounted backplanes attached thereto. A plurality of horizontally stacked substrates are coupled by connectors to the backplanes, with enough clearance between adjacent substrates to ensure heat dissipating air or fluid flow between the substrates. Typically, the substrates are multi-chip modules having a plurality of logic and interconnect chips attached at die mounting locations. Preferably, the logic and interconnect chips are attached to the substrate using flip TAB frames. The substrate includes a pattern interconnect for connecting together all of the chips. The logic chip is based on a standard 10K-50K gate array design with 100 micron pad spacing. The interconnect chip uses an interconnect pattern to connect the logic chips. The interconnect chip uses a lead placement identical to the logic chip, so that a single TAB frame can be used for both chips.

Abstract: A multi-chip module wherein electrical components, such as integrated circuit devices, are packaged in a three dimensional arrangement. The multi-chip module includes a first, or upper, substrate including a signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected to the signal layer. The module further includes a second, or internal, substrate, also including a first signal layer formed on the top surface of the substrate and at least one integrated circuit device mounted to the top surface of the substrate and electrically connected with the signal layer formed on the top surface of the second substrate. The second substrate includes a cavity through the substrate corresponding to each integrated circuit device mounted thereto.

Abstract: A bar code scanner diagnostic method which may be performed at a retail site or during the burn-in phase of manufacturing. The method includes the steps of applying power to the scanner, reading a bar code label by the scanner, determining whether the bar code label is a diagnostic bar code label, reading the diagnostic bar code label by the scanner a first predetermined number of times within a predetermined period of time if the bar code label is the diagnostic bar code label, determining scanner failures which occurred during the reading of the diagnostic bar code label, logging the failures which occurred during reading of the diagnostic bar code label, cycling power to the scanner after the predetermined time period, and performing the reading through cycling steps a second predetermined number of times. Logged failures may be downloaded to a terminal coupled to the scanner and printed by a printer coupled to the terminal.

Abstract: A method and system for reducing pass-through current. The amount of simultaneous current flow through p-channel and n-channel devices of a CMOS inverter is reduced. This results in an increase in the power efficiency of CMOS oscillators, inverters, gates and other CMOS circuits. Another benefit of this invention is the increase of the output signal magnitude. This increase in the output signal with the lower power consumption yields a significantly higher efficiency of the CMOS circuit such as an oscillator.

Abstract: The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centroids, which are themselves distributed symmetrically over the IC. The invention allows individual digital transistors to be connected into a larger, composite, analog transistor.

Abstract: A disk drive within a disk array is utilized to capture the original image of data blocks that are updated, i.e., written over, through normal array processes during backup operations. The method captures original data images in a manner that allows the array to be restored to the state that existed at the initiation of the backup process. During execution of backup procedures data is moved in logical block sequence (0 to N) from the array to a backup device, such as a magnetic tape backup device, continuing until all array data has been transferred. Should a write request be received by the disk array controller during backup, the block address associated with the write request is checked to determine if the original data at that address has been written to the backup device. If the original data residing at the target block address has been written to the backup device the write request is scheduled for execution by the array controller.

Abstract: An I/O transceiver circuit for use on each integrated circuit of a multi-chip module that controls the threshold voltage of the receiver portion and also controls the output resistance of the transmitter portion. Control of the threshold voltage allows operation of the circuit at low voltage levels and with relative immunity from process and temperature variations. Control of the output resistance allows operation without characteristically terminated I/O lines between multi-chip modules, thereby saving power otherwise wasted in the terminating resistors. Control of the threshold voltage is achieved by means of a reference circuit. Control of the output resistance is achieved by a phase-locked-loop arrangement. Further, the I/O transceiver circuit may also have a state where it clamps noise pulses on its I/O line.