Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.

Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.

Abstract: In a processing system including a plurality of graphics processing units (GPUs), the GPUs transfer compressed graphics streams composed of blocks of graphics data to one another. Some blocks of a compressed graphics stream, or parts thereof, may contain both compressed graphics data and meaningless data (referred to as data structure padding, or padding) that is used to align the graphics data, and some blocks may contain only padding. Before transferring a compressed graphics resource from one GPU to another GPU, the sending GPU compacts the compressed graphics resource by filtering out padding from the compressed graphics stream prepared for the transfer.

Abstract: A texture decompression method is described. The method comprises receiving a compressed texture block, determining a partition of pixels used for the compressed texture block, wherein the partition includes one or more disjoint subsets into which data in the compressed texture block is to be unpacked, unpacking data for each subset based on the determined partition, and decompressing each of the one or more disjoint subsets to form an approximation of an original texture block.

Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.

Abstract: Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.

Abstract: Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.

Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.

Abstract: Systems, apparatuses, and methods for compressing pixel data are disclosed. In one embodiment, if a block of pixel data is equal to a constant value, a processor compresses the block down to a metadata value which specifies the constant value for the entire block of pixel data. The processor also detects if the constant value is equal to a video specific typical minimum or maximum value. In another embodiment, the processor receives a plurality of M-bit pixel components which are most significant bit aligned in N-bit containers. Next, the processor shifts the M-bit pixel components down into least significant bit locations of the N-bit containers. Then, the processor converts the N-bit containers into M-bit containers. Next, the processor compresses the M-bit containers to create a compressed block of pixel data which is then stored in a memory subsystem.

Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.

Abstract: Techniques are provided for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.

Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.

Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.

Abstract: A processing device for use with a video conferencing network is provided. The processing device includes memory configured to store data and a processor. The processor is configured to determine a first sampling phase for a portion of first video data and chrominance sub-sample the portion of first video data using the first sampling phase. The processor is also configured to encode the sub-sampled portion of first video data and decode a sub-sampled, encoded portion of second video data. The processor is further configured to determine a second sampling phase at which the portion of second video data is chrominance sub-sampled and chrominance up-sample the portion of second video data using the second sample phase.

Abstract: A data segmenter is configured to determine indices using numbers of most significant bits (MSBs) of fractional values of floating-point representations of component values of an input color that are selected based on exponent values of the floating-point representations. The component values are defined according to a source gamut. The data segmenter is also configured to determine offsets associated with the indices using subsets of the fractional values. An interpolator configured to map the input color to an output color defined according to a destination gamut based on a location in a three-dimensional (3-D) look up table (LUT) indicated by the indices and offsets.

Abstract: Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.

Abstract: The present disclosure presents methods, apparatuses, and systems to bolster communication security, and more particularly to utilize a constant time cryptographic co-processor engine for such communication security. For example, the disclosure includes a method for secure communication, comprising receiving encrypted data at a receiving device; obtaining a randomization for at least one bit of the encrypted data; modifying an execution of a cryptographic algorithm on the at least one bit to obtain a randomized cryptographic algorithm based on the randomization; and executing the randomized cryptographic algorithm on the at least one bit of encrypted data to recover original data associated with the encrypted data.

Abstract: In one form, a data transmission system includes transmission and reception circuits. The transmission circuit includes a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage, a second driver having an input for receiving the I/O power supply voltage, an output, and a positive power supply terminal for receiving the I/O power supply voltage, and a third driver having an input for receiving the I/O ground voltage, an output, and a negative power supply terminal coupled to the I/O ground voltage. The reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of the second and third drivers, and receives a signal from the output of the first driver using the reference voltage.

Abstract: A system including a gasket communicatively coupled between a unified northbridge (UNB) having a cache coherent interconnect (CCI) interface and a processor having an Advanced eXtensible Interface (AXI) coherency extension (ACE). The gasket is configured to translate requests from the processor that include ACE commands into equivalent CCI commands, wherein each request from the processor maps onto a specific CCI request type. The gasket is further configured to translate ACE tags into CCI tags. The gasket is further configured to translate CCI encoded probes from a system resource interface (SRI) into equivalent ACE snoop transactions. The gasket is further configured to translate the memory map to inter-operate with a UNB/coherent HyperTransport (cHT) environment. The gasket is further configured to receive a barrier transaction that is used to provide ordering for transactions.

Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.