Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.

Abstract: The present disclosure relates to a method and system for content presentation in a main processor shutoff mode. A method for content presentation includes transferring content to at least one of a co-processor and storage accessible by the co-processor and shutting off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage. The content may include at least one of multimedia data, text data, and image data. A disclosed system includes a main processor in communication with a co-processor. The main processor includes data transfer logic operative to transfer the content and to shut off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: An apparatus includes a unified system/graphics memory and a memory controller. The memory controller is operative to receive client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing the unified system/graphics memory. The memory controller is operative to provide access to the plurality of memory channels, in parallel, by the CPU and at least one client of the one or more clients. The memory controller is operative to prioritize the CPU data access request to the unified memory over the client data access requests to the unified memory and control the plurality of memory channels to access, in parallel, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.

Abstract: The present disclosure is directed to techniques for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.

Abstract: An apparatus and methods for modifying gradation in an image frame determine a blend factor indicating a first weighting associated with a previously processed portion of the image frame. The apparatus and methods generate a weighted value associated with a current region of the image frame based on the current region of the image frame and based on applying the first weighting to the previously processed portion of the image frame so as to modify the gradation in the image frame.

Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.

Abstract: A processing apparatus is provided that includes an encoder configured to encode current frames of video data using previously encoded reference frames and perform motion searches within a search window about each of a plurality of co-located portions of a reference frame. The processing apparatus also includes a processor configured to determine, prior to performing the motion searches, which locations of the reference frame to reload the search window according to a threshold number of search window reloads using predicted motions of portions of the reference frame corresponding to each of the locations. The processor is also configured to cause the encoder to reload the search window at the determined locations of the reference frame and, for each of the remaining locations of the reference frame, slide the search window in a first direction indicated by the location of the next co-located portion of the reference frame.

Abstract: An image rendering unit (IRU) of a device determines the dynamic frame rate capabilities (DFRCs) of a display and an image frame rate of content to be displayed. Preferably, the DFRCs are stored in a storage device deployed within the display itself. Based on the DFRCs and the image frame rate for the content, the IRU determines an updated frame rate and thereafter provides the content to the display at the updated frame rate. Where control of power consumption is desired, selection of a reduced frame rate can effect a power savings. In this manner, the present invention provides flexible control over display frame rates and/or power consumption of the device.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: Briefly, methods and apparatus to provide image content to, and display image content on, variable refresh rate displays with reduced input lag. The methods and apparatus allow for image tearing, or the displaying of image content from more than one video frame, when the render rate of a provided video frame falls outside the display refresh rate range of a variable refresh rate display when the display is refreshing with a previous frame (e.g. the display is in active refresh), thus reducing the input lag of the content of the provided video frame. The methods and apparatus may also prevent image tearing when the render rate of provided video frames is within the display refresh rate range of a display.

Abstract: A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.

Abstract: Described is a system and method for dynamically changing a resolution level at a frame level based on runtime pre-encoding analysis of content in a video stream. A video encoder continuously analyzes the content during runtime, and collects statistics and/or characteristics of the content before encoding it. This classifies the frame among pre-defined categories of content, where every category has its own bitrate/resolution relation. The runtime encoding resolution is dynamically dependent on the target bitrate and the collected statistics and/or characteristics of the content. This achieves a high quality encode for sequences that are composed of scenes with various content complexity levels for different frames in the video streams.

Abstract: Systems, apparatuses, and methods for implementing a parallel Huffman decoding scheme are disclosed herein. A system with a plurality of execution units receives a Huffman encoded bitstream. The system partitions the encoded bitstream into a plurality of chunks. Each execution unit is assigned to decode a separate chunk of the encoded bitstream as well as an extra portion of an adjacent chunk. With this approach, the decoding of the bitstream overlaps for a programmable amount of data at each chunk boundary since each execution unit, excluding the first execution unit decoding the first chunk of the bitstream, will likely decode a certain number of symbols incorrectly at the beginning of the chunk since the chunk boundaries will not be aligned with symbol boundaries. The system determines, from the decoded extra portion at each chunk boundary, where incorrectly decoded ends and where correctly decoded data begins for each decoded chunk.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: Methods and apparatus that allow encoding of video data in pipelined encoder architectures with reduced encoding performance penalty. The methods and apparatus encode video data without the need to flush the data pipeline and re-encode macroblocks, thus saving time and resulting in an increase in the encoder's throughput. In one embodiment, macroblocks are encoded in a data pipeline to form a first video slice of a plurality of video slices. Once a macroblock overshoot condition occurs, the overshooting macroblock is determined and a second video slice is formed that includes at least one of the overshooting macroblock and the encoded macroblocks without re-encoding the included overshooting macroblock and encoded macroblocks. For example, a second video slice may be formed from the overshooting macroblock, and any remaining encoded macroblocks, that do not form the first video slice.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract: One or more components of a video display device such as a television set can be powered down in response to a determination that a video input source has been paused. The video signal provided by the video input source can be analyzed to determine whether the video source is paused. When the video input source is no longer paused, the powered down components can be restored to fill power operation.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: A method of manufacturing is provided that includes singulating a circuit board from a substrate of plural of the circuit boards, wherein the circuit board is shaped to have four corner hollows. The corner hollows may be various shapes.