Abstract: A method and a graphics control and monitoring system are described. The graphics control and monitoring system is configurable and is equipped with a control and processing device, a computer, a data acquisition device, and a display. The control and processing device is equipped with a field programmable device that is configurable to work with a variety of data acquisition devices. The control and processing device receives data collected by the data acquisition device and processes the data. Further, graphics processing is performed by the processor which can be a central processing unit (CPU), a graphics processing unit (GPU), general purpose computation on GPU (GPGPU) that is equipped with parallel computation capability, among others. After processing, display data is provided to a display.

Abstract: A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core.

Abstract: The present disclosure relates to a method and system for providing an image for display on a monitor. A method for providing an image for display includes detecting an exclusive display mode. In the exclusive display mode, an application is blocked from display on a monitor. In response to detecting the exclusive display mode, a composited surface is generated that comprises display data of a blocked application surface and display data of an exclusive application surface. A disclosed system includes a display mode detector that detects an exclusive display mode and a surface compositing module that causes a generation of a composited surface.

Abstract: A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform.

Abstract: Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors.

Abstract: Methods and apparatus for enabling multiple user participation with a single multimedia computing platform and multiple displays. In particular, the methods enable multi-display rendering. For example, in a gaming environment, each user has the ability to select a particular view of the game that maybe different from other users and is private to that user. A system has a single multimedia computing platform with wired, wireless or combinations thereof. In a multiuser multiple display configuration, an application designates and renders particular or different frames to each of the users that may not be seen by the other users. Each frame is rendered from the perspective of the specific user or based on user selection. A display controller directs the frames to the appropriate displays. A video encoder engine encodes the frames and transmits the compressed frames to the appropriate wireless displays.

Abstract: The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.

Abstract: Power management for a processing system that has multiple processing units, (e.g., multiple graphics processing units (GPUs), is described herein. The processing system includes a power manager that obtains performance, power, operational or environmental data from a power management unit associated with each processor (e.g., GPU). The power manager determines, for example, an average value with respect to at least one of the performance, power, operational or environmental data. If the average value is below a predetermined threshold for a predetermined amount of time, then the power manager notifies a configuration manager to alter the number of active processors (e.g., GPUs), if possible. The power may then be distributed among the remaining GPUs or other processors, if beneficial for the operating and environmental conditions.

Abstract: A method and apparatus for creating one or more themed user interfaces (UI) each capable of displaying content unique to the theme selected. This may allow the use of the one or more display configurations for themed content. A device may be associated with a UI, which is capable of displaying content. One or more display configurations associated with one or more themes may be created. Upon selection of a particular theme, content specific to the particular theme is displayed via the associated display configuration.

Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.

Abstract: A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.

Abstract: A device and method for unobtrusively conducting security access checks via biometric data. The device and method obtains biometric data in response to a request for content and initiates a security clearance process that is substantially unobservable to an individual with clearance to access the requested content.

Abstract: Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed.

Abstract: According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.

Abstract: Provided is a method and system for preloading a cache on a graphical processing unit. The method includes receiving a command message, the command message including data related to a portion of memory. The method also includes interpreting the command message, identifying policy information of the cache, identifying a location and size of the portion of memory, and creating a fetch message including data related to contents of the portion, wherein the fetch message causes the cache to preload data of the portion of memory.

Abstract: A method and apparatus for extending the display area of a source device (SD) to one or more target devices (TDs), are described. According to a method, information that may be displayed at the SD is transmitted to the one or more TDs. At the TDs, the information is displayed and manipulated by a user. An indication of the user's manipulations of the information is received at the SD where the information is physically updated. The SD transmits the updated information to the one or more TDs in order to synchronize the information displayed by the one or more TDs with the transmitted information.

Abstract: A method and system for video processing is disclosed. A device driver interface (DDI) call for flipping or updating an overlay may be skipped or ignored, and may not be used by a user mode driver to pass overlay properties to a kernel mode driver (KMD). Instead, the overlay properties may be passed to the KMD at rendering time during a DDI call for rendering. The user mode driver may call a DDI for rendering an overlay frame while simultaneously passing the overlay property data to the KMD. The KMD may store the overlay property data in an overlay flip queue, program the overlay hardware per the overlay property data stored in the overlay flip queue, and flip the overlay in response to the vertical synchronization deferred procedure call.

Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: A device and method for playing digital video are disclosed. The device includes multiple graphics processing units. The method involves using the multiple graphics processors to decode and output compressed audiovisual stream to a display and a speaker. Audiovisual bit streams possibly containing multi-stream video are efficiently decoded and displayed by sharing decoding-related tasks among multiple graphical processing units.

Abstract: Method and apparatus for centralized timestamp processing is described herein. A graphics processing system includes multiple graphics engines and a timestamp module. For each task, a graphics driver assigns the task to a graphics engine and writes a task command packet to a memory buffer associated with the graphics engine. The graphics driver also writes a timestamp command packet for each task to a timestamp module memory buffer. A command processor associated with the graphics engine signals the timestamp module memory buffer upon completion of the task. If the read pointer is at the appropriate position in the timestamp module memory buffer, the timestamp module/timestamp module memory buffer executes the timestamp command packet and writes the timestamp to a timestamp memory. The timestamp memory is accessible by the graphics driver.