Abstract: A system and method for texture decompression is described. The method comprises receiving a first compressed texture block including two or more disjoint subsets of data and decompressing the first compressed texture block. The decompressing includes decompressing the two or more disjoint subsets in the first compressed texture block to form texels. The two or more disjoint subsets include a first disjoint subset comprising a first set of color endpoints and a second disjoint subset comprising a second set of color endpoints.

Abstract: A technique for generating a trained discriminator is provided. The technique includes applying one or more of a glitched image or an unglitched image to a discriminator; receiving classification output from the discriminator; adjusting weights of the discriminator to improve classification accuracy of the discriminator; applying noise to a generator; receiving an output image from the generator; applying the output image to the discriminator to obtain a classification; and adjusting weights of one of the discriminator or the generator to improve ability of the generator to reduce classification accuracy of the discriminator, based on the classification.

Abstract: Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.

Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.

Abstract: Some implementations provide systems, devices, and methods for implementing a cache replacement policy. A memory request is issued for attribute information associated with a node in an acceleration data structure. The attribute information associated with the node is inserted into a cache entry of the cache and an age associated with the cache entry is set to a value based on the attribute information, in response to the memory request causing a cache miss.

Abstract: A power supply circuit is provided for supplying power from multiple peripheral power supplies to a data processor. The power supply circuit includes a power bus, a plurality of load voltage converters each including an input coupled to the power bus and an output coupled to a respective one of multiple subsystems of the data processor, a plurality of input voltage converters each including an input for coupling to a respective one of multiple peripheral power supply voltages and an output coupled to the power bus, and a feedback control circuit having an input coupled to the power bus and a plurality of outputs coupled to respective ones of the input voltage converters for controlling a current draw of the respective input voltage converter.

Abstract: An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.

Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical inference application are disclosed. A system includes a safety-critical inference application, a safety monitor, and an inference accelerator engine. The safety monitor receives an input image, test data, and a neural network specification from the safety-critical inference application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and neural network specification to the inference accelerator engine which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the inference accelerator engine and covers faults only observable at the network level.

Abstract: Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.

Abstract: The present disclosure relates to techniques for facilitating communication and memory transfer between PCIe devices that permit access to an entire address space even though a limited address space is exposed and/or visible via the PCIe BAR registers. To this end, the present disclosure aims to permit memory transfer of large blocks of memory from one device to another including memory invisible to the system (i.e. not exposed via PCIe BAR registers). For example, in some embodiments, a data packet may be received at a port associated with a processor interconnect. The data packet includes a header which contains a first address associated with the port. In response to identifying the first address from the first data packet at the port, the data packet is decoded. During the decoding process, a second address is identified in a payload of the data packet.

Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: Systems and methods are disclosed that automatically generating a gameplay recording from an application. Techniques are provided to extract data from a buffer, the extracted data are associated with the application; to detect, based on a signature associated with the extracted data, the occurrence of an event; and upon detection of the occurrence of the event, to generate the gameplay recording from an output of the application.

Abstract: An electronic device, including a compression subsystem with a comparator, a history buffer, a match detector, and a command generator, performs operations for generating compressed data from original data. The compression subsystem, starting in each cycle of a clock, processes a search string that is copied from original data to generate commands for compressed data. For processing each search string, the comparator compares each of N substrings from the search string with stored data from the history buffer to find matches between the substrings and the stored data. The match detector then determines a longest match for each of the substrings. The command generator next selectively outputs commands for the compressed data based on the longest matches for the substrings.

Abstract: A display system supports variable refresh rates that include a plurality of refresh rates. A source such as a graphics processing unit (GPU) provides frames to the display system at a selected one of the refresh rates. The refresh rates are factored into a corresponding plurality of prime factors. A plurality of numbers of lines per frame in frames provided at the plurality of refresh rates is determined based on one or more ratios of the plurality of refresh rates, the plurality of prime factors, and a line rate for providing frames to the display system at the plurality of refresh rates. The source then selectively provides frames to the display system at one refresh rate of the plurality of refresh rates using the same line rate regardless of which refresh rate is chosen. Furthermore, the number of lines per frame is an integer for frames provided at the refresh rates.

Abstract: A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

Abstract: A method of save-restore operations includes monitoring, by a power controller of a parallel processor (such as a graphics processing unit), of a register bus for one or more register write signals. The power controller determines that a register write signal is addressed to a state register that is designated to be saved prior to changing a power state of the parallel processor from a first state to a second state having a lower level of energy usage. The power controller instructs a copy of data corresponding to the state register to be written to a local memory module of the parallel processor. Subsequently, the parallel processor receives a power state change signal and writes state register data saved at the local memory module to an off-chip memory prior to changing the power state of the parallel processor.

Abstract: An encoding method is provided which includes receiving a plurality of images, obtaining values of elements in a portion of the images, sorting the elements according to different values of the elements, sorting the elements according to a number of occurrences of the different values and encoding the elements using a subset of the different values having corresponding numbers of occurrences that are higher than corresponding numbers of occurrences of other values. Examples also include a processing device and method for use with palette mode encoding in which the elements are a portion of pixels in images and the values are color values of the portion of pixels in the images.

Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.

Abstract: A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.