Patents Assigned to ATI Technologies ULC
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Patent number: 11714766Abstract: An address translation buffer or ATB is provided for emulating or implementing the PCIe (Peripheral Component Interface Express) ATS (Address Translation Services) protocol within a PCIe-compliant device. The ATB operates in place of (or in addition to) an address translation cache (ATC), but is implemented in firmware or hardware without requiring the robust set of resources associated with a permanent hardware cache (e.g., circuitry for cache control and lookup). A component of the device (e.g., a DMA engine) requests translation of an untranslated address, via a host input/output memory management unit for example, and the response (including a translated address) is stored in the ATB for use for a single DMA operation (which may involve multiple transactions across the PCIe bus).Type: GrantFiled: December 29, 2020Date of Patent: August 1, 2023Assignee: ATI Technologies ULCInventors: Philip Ng, Vinay Patel
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Patent number: 11715253Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.Type: GrantFiled: June 14, 2021Date of Patent: August 1, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
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Patent number: 11714442Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignees: ATI Technologies ULC, Advanced Micro Devices Inc.Inventors: Meeta Surendramohan Srivastav, Ashwini Chandrashekhara Holla, Alex Sabino Duenas, Xinzhe Li, Michael John Austin, Indrani Paul, Sriram Sambamurthy
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Patent number: 11710209Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: May 3, 2022Date of Patent: July 25, 2023Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Patent number: 11703931Abstract: A processing apparatus is provided which includes memory configured to store hardware parameter settings for each of a plurality of applications. The processing apparatus also includes a processor in communication with the memory configured to store, in the memory, the hardware parameter settings, identify one of the plurality of applications as a currently executing application and control an operation of hardware by tuning a plurality of hardware parameters according to the stored hardware parameter settings for the identified application.Type: GrantFiled: December 24, 2020Date of Patent: July 18, 2023Assignee: ATI Technologies ULCInventors: Shahriar Pezeshgi, Jun Huang, Mohammad Hamed Mousazadeh, Alexander S. Duenas
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Patent number: 11703930Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: GrantFiled: July 21, 2021Date of Patent: July 18, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Patent number: 11699408Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.Type: GrantFiled: December 22, 2020Date of Patent: July 11, 2023Assignee: ATI Technologies ULCInventors: Arshad Rahman, Rajeevan Panchacharamoorthy, Boris Ivanovic
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Patent number: 11693813Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: GrantFiled: May 30, 2019Date of Patent: July 4, 2023Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
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Publication number: 20230205584Abstract: A disclosed technique includes allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Zhuo Chen, Steven J. Tovey
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Publication number: 20230209064Abstract: Methods and devices are provided for encoding a video stream which comprise encoding a plurality of frames of video acquired from different points of view, generating statistical values for the frames of video determined from values of pixels of the frames, generating, for each of the plurality of frames, a perceptual hash value based on statistical values of the frame and encoding a current frame comprising video acquired from a corresponding one of the different points of view using a previously encoded reference frame based on a similarity of perceptual hashes of the current frame and the previously encoded reference frame.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: ATI Technologies ULCInventors: Sunil Gopal Koteyar, Sonu Thomas, Ihab M. A. Amer, Haibo Liu
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Patent number: 11687251Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.Type: GrantFiled: September 28, 2021Date of Patent: June 27, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Joseph L. Greathouse, Alan D. Smith, Francisco L. Duran, Felix Kuehling, Anthony Asaro
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Publication number: 20230198528Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kaushik Mazumdar, Joyce Cheuk Wai Wong, Naeem Ibrahim Ally, Stephen Victor Kosonocky
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Publication number: 20230195191Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kaushik Mazumdar, Miguel Rodriguez, Mikhail Rodionov, Stephen Victor Kosonocky
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Patent number: 11682465Abstract: An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.Type: GrantFiled: September 30, 2021Date of Patent: June 20, 2023Assignee: ATI Technologies ULCInventors: Zheng Gong, Jiao Wang, Zhenhua Yang
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Publication number: 20230187379Abstract: An electronic device includes a substrate, an electronic component, a structure, and an adhesive. The substrate has a proximal surface. The electronic component includes at least one die, wherein the electronic component is attached to the substrate. The structure has a proximal surface adjacent to proximal surface of the substrate. A feature extends from the proximal surface of the structure or the substrate, and the adhesive contacts the feature and the proximal surfaces of the structure and the substrate. In another aspect, a process of forming the electronic device can include applying the adhesive, placing the substrate and structure adjacent to each other, wherein the adhesive contacts the feature and the proximal surfaces of the substrate and the substrate, and curing the adhesive.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Applicant: ATI Technologies ULCInventor: Roden Topacio
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Publication number: 20230178126Abstract: A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.Type: ApplicationFiled: June 30, 2022Publication date: June 8, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Aaron John Nygren, Michael John Litt, Karthik Gopalakrishnan, Tsun Ho Liu
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Patent number: 11662798Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.Type: GrantFiled: July 30, 2021Date of Patent: May 30, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
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Patent number: 11657483Abstract: There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.Type: GrantFiled: October 13, 2020Date of Patent: May 23, 2023Assignee: ATI Technologies ULCInventors: Jie Zhou, David I. J. Glen
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Publication number: 20230156205Abstract: A system and method for texture decompression is described. The method comprises receiving a first compressed texture block including two or more disjoint subsets of data and decompressing the first compressed texture block. The decompressing includes decompressing the two or more disjoint subsets in the first compressed texture block to form texels. The two or more disjoint subsets include a first disjoint subset comprising a first set of color endpoints and a second disjoint subset comprising a second set of color endpoints.Type: ApplicationFiled: January 19, 2023Publication date: May 18, 2023Applicant: ATI Technologies ULCInventors: Konstantine Iourcha, Andrew S.C. Pomianowski
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Publication number: 20230156250Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (AN) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.Type: ApplicationFiled: January 6, 2023Publication date: May 18, 2023Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Lei Zhang, Gabor Sines, Khaled Mammou, David Glen, Layla A. Mah, Rajabali M. Koduri, Bruce Montag
