Patents Assigned to ATI Technologies
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Patent number: 10365824Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.Type: GrantFiled: April 24, 2017Date of Patent: July 30, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Anthony Asaro
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Patent number: 10368108Abstract: A video source, a display and a method of processing multilayered video are disclosed. The video source decodes a multilayered video bit stream to transmit synchronized streams of decompressed video images and corresponding overlay images to an interconnected display. The display receives separate streams of video and overlay images. Transmission and reception of corresponding video and overlay images is synchronized in time. A video image received in the display can be selectively processed separately from its corresponding overlay image. The video image as processed at the display is later composited with its corresponding overlay image to form an output image for display.Type: GrantFiled: December 21, 2012Date of Patent: July 30, 2019Assignee: ATI Technologies ULCInventor: David I. J. Glen
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Patent number: 10368079Abstract: A single source image encoder encodes more than one display stream, such as multiple display streams each for a different display or multiple display streams for the same display, using multiple index color history (ICH) buffers. As applied to a DSC encoder, the same DSC encoder is used to encode more than one DSC compliant display stream. Multiple encoded display bitstreams are output as multiple display data streams to a plurality of displays. Such a configuration can significantly reduce the area cost of an integrated circuit that employs an image encoder since additional encoders are eliminated.Type: GrantFiled: March 31, 2017Date of Patent: July 30, 2019Assignee: ATI Technologies ULCInventors: David Glen, Nicholas Chorney
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Patent number: 10368087Abstract: A processing apparatus is provided that includes an encoder configured to encode current frames of video data using previously encoded reference frames and perform motion searches within a search window about each of a plurality of co-located portions of a reference frame. The processing apparatus also includes a processor configured to determine, prior to performing the motion searches, which locations of the reference frame to reload the search window according to a threshold number of search window reloads using predicted motions of portions of the reference frame corresponding to each of the locations. The processor is also configured to cause the encoder to reload the search window at the determined locations of the reference frame and, for each of the remaining locations of the reference frame, slide the search window in a first direction indicated by the location of the next co-located portion of the reference frame.Type: GrantFiled: September 20, 2016Date of Patent: July 30, 2019Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Ihab Amer, Gabor Sines, Edward Harold, Jinbo Qiu, Lei Zhang, Yang Liu, Zhen Chen, Ying Luo, Shu-Hsien Wu, Zhong Cai
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Publication number: 20190229736Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Stephen Victor Kosonocky, Mikhail Rodionov, Joyce Cheuk Wai Wong
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Patent number: 10360177Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.Type: GrantFiled: June 22, 2016Date of Patent: July 23, 2019Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev
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Patent number: 10353859Abstract: A method for allocating registers in a compute unit of a vector processor includes determining a maximum number of registers that are to be used concurrently by a plurality of threads of a kernel at the compute unit. The method further includes setting a mode of register allocation at the compute unit based on a comparison of the determined maximum number of registers and a total number of physical registers implemented at the compute unit.Type: GrantFiled: February 14, 2017Date of Patent: July 16, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: YunPeng Zhu, Jimshed Mirza
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Patent number: 10339068Abstract: Systems, apparatuses, and methods for implementing a virtualized translation lookaside buffer (TLB) are disclosed herein. In one embodiment, a system includes at least an execution unit and a first TLB. The system supports the execution of a plurality of virtual machines in a virtualization environment. The system detects a translation request generated by a first virtual machine with a first virtual memory identifier (VMID). The translation request is conveyed from the execution unit to the first TLB. The first TLB performs a lookup of its cache using at least a portion of a first virtual address and the first VMID. If the lookup misses in the cache, the first TLB allocates an entry which is addressable by the first virtual address and the first VMID, and the first TLB sends the translation request with the first VMID to a second TLB.Type: GrantFiled: April 24, 2017Date of Patent: July 2, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Anthony Asaro
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Patent number: 10334276Abstract: An encoder encodes pixels representative of a picture in a multimedia stream, generates a first approximate signature based on approximate values of pixels in a reconstructed copy of the picture, and transmits the encoded pixels and the first approximate signature. A decoder receives a first packet including the encoded pixels and the first approximate signature, decodes the encoded pixels, and transmits a first signal in response to comparing the first approximate signature and a second approximate signature generated based on approximate values of the decoded pixels. If a corrupted packet is detected, the multimedia application requests an intra-coded picture in response to the first approximate signature differing from the second approximate signature. The second signal instructs the decoder to bypass requesting an intra-coded picture and to continue decoding received packets in response to the first approximate signature being equal to the second approximate signature.Type: GrantFiled: December 28, 2015Date of Patent: June 25, 2019Assignee: ATI Technologies ULCInventors: Ihab Amer, Gabor Sines, Khaled Mammou, Haibo Liu, Edward Harold, Lei Zhang, Fabio Gulino, Ehsan Mirhadi, Ho Hin Lau
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Publication number: 20190188822Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Applicant: ATI Technologies ULCInventors: Syed Arshad Rahman, Michael I. Hvizdos, Leonid Shamis
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Patent number: 10324860Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.Type: GrantFiled: September 5, 2017Date of Patent: June 18, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
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Patent number: 10319063Abstract: In a processing system including a plurality of graphics processing units (GPUs), the GPUs transfer compressed graphics streams composed of blocks of graphics data to one another. Some blocks of a compressed graphics stream, or parts thereof, may contain both compressed graphics data and meaningless data (referred to as data structure padding, or padding) that is used to align the graphics data, and some blocks may contain only padding. Before transferring a compressed graphics resource from one GPU to another GPU, the sending GPU compacts the compressed graphics resource by filtering out padding from the compressed graphics stream prepared for the transfer.Type: GrantFiled: February 24, 2017Date of Patent: June 11, 2019Assignee: ATI Technologies ULCInventor: Guennadi Riguer
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Patent number: 10318340Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.Type: GrantFiled: December 31, 2014Date of Patent: June 11, 2019Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Gabriel H. Loh, Mauricio Breternitz
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Publication number: 20190174140Abstract: A texture decompression method is described. The method comprises receiving a compressed texture block, determining a partition of pixels used for the compressed texture block, wherein the partition includes one or more disjoint subsets into which data in the compressed texture block is to be unpacked, unpacking data for each subset based on the determined partition, and decompressing each of the one or more disjoint subsets to form an approximation of an original texture block.Type: ApplicationFiled: January 25, 2019Publication date: June 6, 2019Applicant: ATI Technologies ULCInventors: Konstantine Iourcha, Andrew S. C. Pomianowski
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Patent number: 10310266Abstract: Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.Type: GrantFiled: February 10, 2016Date of Patent: June 4, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Khaled Mammou, Layla A. Mah
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Patent number: 10310985Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.Type: GrantFiled: June 26, 2017Date of Patent: June 4, 2019Assignee: ATI Technologies ULCInventors: Dhirendra Partap Singh Rana, Conrad Lai, Jeffrey G. Cheng
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Patent number: 10311236Abstract: Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.Type: GrantFiled: November 22, 2016Date of Patent: June 4, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kathirkamanathan Nadarajah, Oswin Housty, Sergey Blotsky, Tan Peng, Hary Devapriyan Mahesan
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Patent number: 10304155Abstract: Systems, apparatuses, and methods for compressing pixel data are disclosed. In one embodiment, if a block of pixel data is equal to a constant value, a processor compresses the block down to a metadata value which specifies the constant value for the entire block of pixel data. The processor also detects if the constant value is equal to a video specific typical minimum or maximum value. In another embodiment, the processor receives a plurality of M-bit pixel components which are most significant bit aligned in N-bit containers. Next, the processor shifts the M-bit pixel components down into least significant bit locations of the N-bit containers. Then, the processor converts the N-bit containers into M-bit containers. Next, the processor compresses the M-bit containers to create a compressed block of pixel data which is then stored in a memory subsystem.Type: GrantFiled: February 24, 2017Date of Patent: May 28, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anthony Chan, Christopher J. Brennan
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Patent number: 10304506Abstract: Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.Type: GrantFiled: November 10, 2017Date of Patent: May 28, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Benjamin Tsien, Bradley Kent, Joyce C. Wong
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Publication number: 20190148345Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Applicant: ATI Technologies ULCInventor: Changyok Park