Patents Assigned to ATI Technologies
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Patent number: 10103837Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.Type: GrantFiled: June 23, 2016Date of Patent: October 16, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Stanley Ames Lackey, Jr., Damon Tohidi, Gerald R. Talbot, Edoardo Prete
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Patent number: 10095295Abstract: A method and apparatus controls power management of a graphics processing core when multiple virtual machines are allocated to the graphics processing core on a much finer-grain level than conventional systems. In one example, the method and apparatus processes a plurality of virtual machine power control setting requests to determine a power control request for a power management unit of a graphics processing core. The method and apparatus then controls power levels of the graphics processing core with the power management unit based on the determined power control request.Type: GrantFiled: December 14, 2011Date of Patent: October 9, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Oleksandr Khodorkovsky, Stephen D. Presant
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Patent number: 10097835Abstract: A method of video encoding is disclosed which is content adaptive. The encoding method is automatically adjusted to optimize the encoding, the adjusting depending on the content of the pictures being encoded. A system for implementing the method and a non-transitory computer-readable storage medium for storing instructions of the method are also disclosed.Type: GrantFiled: March 4, 2015Date of Patent: October 9, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Khaled Mammou, Ihab M. A. Amer, Oleksandr O. Bobrovnik, Vladyslav S. Zakharchenko
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Patent number: 10085017Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.Type: GrantFiled: November 29, 2012Date of Patent: September 25, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Lei Zhang, Ji Zhou, Zhen Chen, Min Yu
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Patent number: 10074600Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.Type: GrantFiled: March 30, 2012Date of Patent: September 11, 2018Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Fei Guo, Feng Zhu, Julius Din, Anwar Kashem, Sally Yeung
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Publication number: 20180246815Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Publication number: 20180246816Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Patent number: 10063834Abstract: A method and apparatus for processing video utilize individually collected image enhancement statistic information from differing processor cores for a same frame or multi-view that are then either shared between the processor cores or used by a third processor core to combine the statistical information that has been individually collected to generate global image-enhancement control information. The global image enhancement control information is based on a global analysis of both left and right eye views for example using the independently generated statistic information for a pair of frames. Respective image output information is produced by each of the plurality of processor cores based on the global image enhancement control information, for display on one or more displays.Type: GrantFiled: September 13, 2011Date of Patent: August 28, 2018Assignee: ATI Technologies ULCInventor: Edward G. Callway
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Patent number: 10056027Abstract: A virtualized DisplayPort (DP) configuration data (DPCD) for multi-stream transport (MST) logical DP end points and non-DP end points allows DPCD configuration for links within a DisplayPort topology which are not configurable using DPCD. A virtualized DPCD may configure a link to an internal display of a MST sink device or a non-DP display to receive data using a dynamic refresh rate (DRR), display stream compression (DSC), panel self-refresh (PSR) and other DPCD configurable features.Type: GrantFiled: November 18, 2016Date of Patent: August 21, 2018Assignee: ATI Technologies ULCInventor: Syed Athar Hussain
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Patent number: 10055857Abstract: A system, method and computer program product to traverse a polygon mesh, partition the polygon mesh into a set of polygon fans based on the traversal order, and tessellate the set of polygon fans into triangles based on the traversal order. This transformation of the polygon mesh into a triangle mesh enables the polygon mesh to be compressed and decompressed using the SC3DMC standard.Type: GrantFiled: August 29, 2014Date of Patent: August 21, 2018Assignee: ATI Technologies ULCInventor: Khaled Mammou
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Patent number: 10043481Abstract: A method and device of over training a connection is provided. Noise is intentionally supplied and added to a signal that is subjected to a link training operation. The link training operation is used to obtain a link between a source device and a receiving device. The device includes a noise source from which noise is obtained and added to a signal to aid in link over-training.Type: GrantFiled: May 18, 2015Date of Patent: August 7, 2018Assignee: ATI Technologies ULCInventor: James D. Hunkins
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Publication number: 20180217844Abstract: A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: John Kalamatianos, Greg Sadowski, Syed Zohaib M. Gilani
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Patent number: 10025721Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.Type: GrantFiled: October 24, 2014Date of Patent: July 17, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Vydhyanathan Kalyanasundharam, Philip Ng, Maggie Chan, Vincent Cueva, Anthony Asaro, Jimshed Mirza, Greggory D. Donley, Bryan Broussard, Benjamin Tsien, Yaniv Adiri
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Patent number: 10021413Abstract: Methods and apparatus for facilitating processing a reference frame to produce an output frame. Motion vector data for a block of reference frame pels estimates the displacement of the reference frame pels from corresponding pels in a prior input frame. Comparison metrics are produced for a pel of the reference frame with respect to that pel and a plurality of neighboring reference frame pels. A first comparison metric is based on a comparison with corresponding pels of a prior output frame that corresponds to the prior input frame as previously processed. A second comparison metric is based on a comparison with corresponding pels of a motion compensated prior output frame derived from applying motion vector data to the pels of the prior output frame. A pel of the output frame that corresponds to the reference frame pel is determined using the first and second comparison metrics.Type: GrantFiled: December 22, 2016Date of Patent: July 10, 2018Assignee: ATI Technologies ULCInventors: Sahar Alipour Kashi, Boris Ivanovic, Allen J. Porter
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Publication number: 20180181340Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) or a discrete GPU (dGPU). In particular, a method is described for transferring data between the first memory architecture and the second memory architecture that bypasses interaction with a system memory of a processor and a root complex. A transfer command is sent from the processor, (or a host agent in the GPU or dGPU), to a first memory architecture controller. The first memory architecture controller initiates the transfer of the data directly between the first memory architecture and the second memory architecture. The method bypasses: 1) a host root complex; and 2) storing the data in the system memory and then having to transfer the data to the second memory architecture or the first memory architecture.Type: ApplicationFiled: December 23, 2016Publication date: June 28, 2018Applicant: ATI Technologies ULCInventor: Nima Osqueizadeh
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Publication number: 20180181518Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.Type: ApplicationFiled: December 23, 2016Publication date: June 28, 2018Applicant: ATI Technologies ULCInventor: Nima Osqueizadeh
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Publication number: 20180181519Abstract: Described herein is a method and system for accessing a block addressable input/output (I/O) device, such as a non-volatile memory (NVM), as byte addressable memory. A front end processor connected to a Peripheral Component Interconnect Express (PCIe) switch performs as a front end interface to the block addressable I/O device to emulate byte addressability. A PCIe device, such as a graphics processing unit (GPU), can directly access the necessary bytes via the front end processor from the block addressable I/O device. The PCIe compatible devices can access data from the block I/O devices without having to go through system memory and a host processor. In an implementation, a system can include block addressable I/O, byte addressable I/O and hybrids thereof which support direct access to byte addressable memory by the host processor, GPU and any other PCIe compatible device.Type: ApplicationFiled: December 23, 2016Publication date: June 28, 2018Applicant: ATI Technologies ULCInventor: Gongxian Jeffrey Cheng
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Publication number: 20180181520Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.Type: ApplicationFiled: April 28, 2017Publication date: June 28, 2018Applicant: ATI Technologies ULCInventor: Nima Osqueizadeh
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Publication number: 20180181488Abstract: Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.Type: ApplicationFiled: December 23, 2016Publication date: June 28, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Mark Fowler, Jimshed Mirza, Anthony Asaro
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Patent number: RE47054Abstract: A multiplexed packetized data stream carrying real-time multimedia programs is received at a first hardware demultiplexer. Based on a user input, a video and timing portion of a program associated with the multiplexed packetized data stream can be stored for subsequent display. One type of subsequent display is time shifted display, where the stored portion of the program is played back while new portions of the program are being stored. During time shifted play back, a second hardware demultiplexer can be used, so that one demultiplexer stores new data and maintains a current clock value while the other decodes and displays the stored data.Type: GrantFiled: December 2, 2016Date of Patent: September 18, 2018Assignee: ATI Technologies ULCInventor: Branko Kovacevic