Abstract: Systems, apparatuses, and methods for performing parallel histogram calculation with application to palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of pixel component value bits of a block of pixels. Then, the encoder selects a first number of the highest pixel count bins from the first histogram. Also, the encoder calculates a second histogram for a second portion of pixel component value bits of the block. The encoder selects a second number of the highest pixel count bins from the second histogram. A third histogram is calculated from the concatenation of bits assigned to the first and second number of bins, and the highest pixel count bins are selected from the third histogram. A palette table is derived based on these highest pixel count bins selected from the third histogram, and the block of pixels is encoded using the palette table.

Abstract: Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

Abstract: A multi-module overhead display assembly for use with a gaming system. The multi-module overhead display assembly has a housing module releasably connected to one or more other housing modules for display of content above a game machine. A mounting structure for the releasably connected housing module is provided to be connectable to a mount system. At least one housing module comprises a controller having a processor and memory storing instructions, which, when executed, cause the processor to individually control each of the housing modules to display the content.

Abstract: Systems, apparatuses, and methods for performing color channel correlation detection are disclosed. A compression engine performs a color channel transform on an original set of pixel data to generate a channel transformed set of pixel data. An analysis unit determines whether to compress the channel transformed set of pixel data or the original set of pixel data based on performing a comparison of the two sets of pixel data. In one scenario, the channel transformed set of pixel data is generated by calculating the difference between a first pixel component and a second pixel component for each pixel of the set of pixel data. The difference is then compared to the original first pixel component for each pixel. If the difference is less than or equal to the original for a threshold number of pixels, then the analysis unit decides to apply the color channel transform prior to compression.

Abstract: Gaming devices and systems incorporating one or more image projectors capable of displaying under control of a video controller. The video controller may be onboard the gaming device, or can be a video controller server in networked communication with an individual gaming device; wherein some cases both such video controllers may be utilized. The video controller(s) have access to one or more image projectors on a gaming device and may respond to different trigger conditions to exercise control over image projectors of respective gaming devices. An onboard video controller in a first gaming device may communicate with two or more additional gaming devices, such as a bank of gaming devices, for controlling image projectors of such devices.

Abstract: Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on an integrated circuit (IC), and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.

Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.

Abstract: Systems, apparatuses, and methods for enabling localized control of link states in a computing system are disclosed. A computing system includes at least a host processor, a communication fabric, one or more devices, one or more links, and a local link controller to monitor the one or more links. In various implementations, the local link controller detects and controls states of a link without requiring communication with, or intervention by, the host processor. In various implementations, this local control by the link controller includes control over the clock signals provided to the link. For example, the local link controller can directly control the frequency of a clock supplied to the link. In addition, in various implementations the link controller controls the power supplied to the link. For example, the link controller can control the voltage supplied to the link.

Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical graphics processing unit (GPU) compute application are disclosed. A system includes a safety-critical GPU compute application, a safety monitor, and a GPU. The safety monitor receives a compute grid, test vectors, and a compute kernel from the safety-critical GPU compute application. The safety monitor generates a modified compute grid by adding extra tiles to the original compute grid, with the extra tiles generated based on the test vectors. The safety monitor provides the modified compute grid and compute kernel to the GPU for processing. The safety monitor determines the likelihood of erroneous processing of the original compute grid by comparing the actual results for the extra tiles with known good results. The safety monitor complements the overall fault coverage of the GPU hardware and covers faults only observable at the application programming interface (API) level.

Abstract: A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.

Abstract: A system and method for texture decompression is described. The method comprises receiving a compressed texture block including two or more disjoint subsets of data and decompressing the compressed texture block. The decompressing includes decompressing each of the two or more disjoint subsets in the compressed texture block to form texels. The two or more disjoint subsets include a first disjoint subset having a first set of color endpoints and a first index value for a first texel, and a second disjoint subset having a second set of color endpoints.

Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.

Abstract: Systems, apparatuses, and methods for remotely adjusting performance and power parameters of a computing device are disclosed. A computing system includes a first computing device connected to a second (remote) computing device. The user uses the second computing device to monitor and adjust parameters, such as a fan speed for a GPU on a video graphics card in the first computing device, while the first computing device executes a parallel data application such as a video game. Additionally, the user uses the second computing device to manage video recorder operations. By using the second computing device to send commands to a graphics driver and a video recorder application, the first computing device's display monitor does not display a user interface during execution of the video game. No video rendering is performed by the video graphics card of the first computing device to generate and control the user interface.

Abstract: Systems, apparatuses, and methods for calculating multi-pass histograms for palette table derivation are disclosed. An encoder calculates a first histogram for a first portion of most significant bits (MSBs) of pixel component values of a block of an image or video frame. Then, the encoder selects a given number of the highest pixel count bins from the first histogram. The encoder then increases the granularity of these selected highest pixel count bins by evaluating one or more additional bits from the pixel component values. A second histogram is calculated for the concatenation of the original first portion MSBs from the highest pixel count bins and the one or more additional bits, and the highest pixel count bins are selected from the second histogram. A palette table is derived based on these highest pixel count bins selected from the second histogram, and the block is encoded using the palette table.

Abstract: An image generation apparatus includes at least a first configuration register that includes first configuration data for configuring parameters of an image processor, at least a second configuration register that includes second configuration data for configuring the parameters of a same image processing pipeline in the image processor, multiplexing logic coupled to the first configuration register and to the second configuration register, control logic that controls the multiplexing logic to in a non-demonstration mode select one of the first or second configuration registers to produce a first image frame and operative in a demonstration mode to provide both the first and second configuration data for the same image processing pipeline of the image processor to use for generating different regions of an image frame.

Abstract: A device is disclosed that includes a battery charge controller having an input removably connected to a power adapter and an output supplying DC current to a battery, a voltage regulator having an input coupled to the output of the battery charge controller and the battery, and a current sensing unit used by the battery charge controller for sensing a charging current to the battery and by the voltage regulator for sensing a discharging current from the battery. Various other methods and systems are also disclosed.

Abstract: The disclosed voltage regulator circuit includes a capacitor bank configured for a first voltage step corresponding to a voltage undershoot, and a shunt circuit configured for a second voltage step exceeding the first voltage step. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

Abstract: In some examples, an apparatus obtains source layer pixels, such as those of a content image and first destination layer pixels, such as those of a destination image. The first destination layer pixels have associated alpha values. The apparatus obtains information that indicates a first blending color format for the alpha values. The first blending color format is different from a first destination layer color format for the first destination layer pixels and an output color format for a display. The apparatus converts the source and/or first destination layer pixels to the first blending color format. The apparatus generates first alpha blended pixels based on alpha blending the source layer pixels with the first destination layer pixels using the associated alpha values. The apparatus provides, for display on the display, the first alpha blended pixels.

Abstract: Power management in a computing device. A driver is registered with an operating system (OS) executing on the computing device to receive information about a position of a user interface control. If the user interface control is moved, the driver receives a notification of the user interface control position and determines a power management intervention based on the position The driver transmits the power management intervention to power control circuitry which sets a power setting of the computing device based on the intervention.