Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.

Abstract: An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.

Abstract: Systems, apparatuses, and methods for detecting personal-space violations in artificial intelligence (AI) based non-player characters (NPCs) are disclosed. An AI engine creates a NPC that accompanies and/or interacts with a player controlled by a user playing a video game. During gameplay, measures of context-dependent personal space around the player and/or one or more NPCs are generated. A control circuit monitors the movements of the NPC during gameplay and determines whether the NPC is adhering to or violating the measures of context-dependent personal space. The control circuit can monitor the movements of multiple NPCs simultaneously during gameplay, keeping a separate score for each NPC. After some amount of time has elapsed, the scores of the NPCs are recorded, and then the scores are provided to a machine learning engine to retrain the AI engines controlling the NPCs.

Abstract: The disclosed computer-implemented method for multi-lane data bus inversion can include receiving data for transmission via a plurality of data lanes, each data lane corresponding to one of a plurality of inversion bits, and, for each data lane within the plurality of data lanes, applying the corresponding inversion bit to each bit within the data lane. Various other methods, apparatuses, and systems are also disclosed.

Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

Abstract: A technique for performing video operations is provided. The technique includes characterizing a frame as a flash frame; setting the flash frame as a non-intra frame; prohibiting encoding of frames other than the flash frame with reference to the flash frame; and applying a positive quantization parameter (“QP”) offset to the flash frame.

Abstract: In a cloud gaming system or other remote video streaming system, a client device and a server coordinate to introduce an adjustable delay in the frame start timing in the frame rendering pipeline at the server to reducing vertical synchronization (VSYNC) presentation latency, and thus reduce overall frame latency. In implementations, the coordination between the client device and the server includes the client device observing the current VSYNC presentation latencies in recently processed video frames reporting this observed VSYNC presentation latency to the server. The server uses this feedback to determine a frame start delay that is then used to introduce a frame start shift for an upcoming frame and subsequent frames, thereby shifting the server rendering and encoding pipeline back so that the resulting video frames are made available to present at the client device closer to their respective VSYNC signal assertions.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: A processing system selects a reset sequence based on a sideband connected configuration of a plurality of processing units. The processing system identifies whether the plurality of processing units is in the sideband connected configuration, so that the plurality of processing units works together on assigned operations. Based on the identification, the processing system selects and executes one of a plurality of available reset sequences. The processing system is thus able to tailor the executed reset sequence for the configuration of the plurality of processing units, thereby reducing the number of overall system resets and improving processing efficiency.

Abstract: A processor for optimizing partial writes to compressed blocks is configured to identify that a write request targets less than an entirety of a compressed block of pixel data, identify, based on a compression key, a compressed segment of the compressed block of pixel data that includes a target of the write request, and decompress, responsive to the write request, only the identified compressed segment of the compressed block of pixel data.

Abstract: According to one embodiment, an alpha-beta titanium alloy comprises, in weight percentages: an aluminum equivalency in the range of about 6.7 to 10.0; a molybdenum equivalency in the range of 0 to 5.0; at least 2.1 vanadium; 0.3 to 5.0 cobalt; titanium; and incidental impurities.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, traversing through a bounding volume hierarchy for a ray to arrive at a well-fit bounding volume that is associated with first node, wherein the first node is one of a traversal node or a procedural node, and wherein the well-fit bounding volume comprises geometry other than a single axis-aligned bounding box for the first node; evaluating the ray for intersection with the well-fit bounding volume; determining whether to execute a first shader program associated with the first node based on the evaluating, wherein the first shader program comprises a traversal shader program or a procedural shader program; and executing or not executing the first shader program based on the determining.

Abstract: A technique for performing ray tracing operations is provided. The technique includes detecting intersection of a ray with a split bounding volume of an instance of a bounding volume hierarchy; determining whether the split bounding volume meets an instance traversal limiting criterion; and continuing BVH traversal based on the determining.

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

Abstract: A distribution system receives data access requests associated with at least two virtual channels over at least two physical data communication channels. The requests are distributed into at least two sequencers of the distribution system based on a virtual channel associated with each request. The distribution system includes at least two memory modules—one for each of the at least two physical data communication channels. Requests stored in the sequencers are written to the memory modules according to a pattern that assigns sequential requests associated with a common virtual channel to a sequential ordering of the memory modules. The requests are then granted by an arbiter of the distribution system by retrieving requests associated with a common virtual channel from the memory modules using the sequential ordering of the memory modules.

Abstract: In one embodiment, an intermediary gaming trusted electronic device for use with an untrusted PED may operate to securely communicate with a gaming apparatus and securely communicate with the associated untrusted PED. The intermediary gaming trusted device is able to support interaction between the gaming apparatus and the associated untrusted PED. In another embodiment, a system to authorize a mobile electronic device to play games of chance may include a gaming system manager and a docking station. The docking station can be configured to: detect whether the mobile electronic device is connected to the docking station; and determine whether the mobile electronic device, or its user, is authorized to play a game of chance on the mobile electronic device.

Abstract: A method of shifting a color temperature of an image on a display is provided which comprises, for each pixel of the image, converting red, green and blue (RGB) components of the pixel in a non-linear light space to hue, saturation, and value (HSV) components of the pixels in an HSV color space, calculating a color temperature shift for the pixel based on the HSV components of the pixel, converting the RGB components of the pixel in the non-linear light space to RGB components of the pixel in a linear light space, modifying the RGB components of the pixel in the linear light space and converting the modified RGB components of the pixel in the linear light space to modified RGB components of the pixel in the non-linear light space.

Abstract: An apparatus and method for providing efficient power management for data transfer protocols between components. A source generates requests and a destination services the requests. The source and destination support a communication protocol that includes both a transfer channel and one or more transaction channels for each type of request. The source and destination rely on a valid signal and a ready signal of the transfer channels to autonomously manage power consumption. The source and destination remove any dependencies on an external power manager and make it unnecessary to add signal extensions to the communication protocol to support power management.