Abstract: Common mode management between a DAC, such as a current-steering DAC, and a transconductance filter in a high-frequency transmission system. In one aspect of the invention, a transmission circuit includes a DAC that provides an analog signal from an input digital signal, and a filter such as a transconductance filter connected to the DAC, the filter receiving the analog signal and filtering the analog signal for transmission. A common mode management circuit connected to the DAC and the transconductance filter provides common mode compatibility in the interface connecting the DAC and the transconductance filter.

Abstract: A method, device, and processor-readable medium for testing semiconductor devices. A method for testing a semiconductor device comprises: a) entering a multi-byte programming mode; b) programming a plurality of bytes, each byte programmed with identical data; and c) verifying each programmed byte one byte at a time, returning to step b) if any byte fails to verify, otherwise waiting for a next command.

Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Abstract: The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the distances between drains, sources, and gates are optimized to reduce resistance and power dissipation. The gates may be arranged in a trapezoidal arrangement in order to maximize a ratio of the gate widths to gate lengths for current driving while reducing resistance and power dissipation.

Abstract: Bit lines of a memory device are arranged by an interleaving of even and odd bit lines and segregated into an even and odd bank. A discharge network discharges the banks alternately. A bit line selection network alternately connects the banks to a sense amplifier. The bank of odd bit lines is discharged just prior to a selection of the bank of even bit lines for reading and vice-versa. Interleaving even and odd bit lines in combination with alternating selection and discharge of banks reduces a cross coupling voltage. A discharge delay ensures that a sense amplifier does not detect any signal during a discharge phase. The discharge delay is much shorter than the cross coupling delay required with no discharge scheme present. Discharging complementary banks of bit lines plus reduced discharge delay ensures that along with a short access time, correct data are detected by the sense amplifier.

Abstract: A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

Abstract: An apparatus and method of speculatively decoding non-memory read commands. A command register and decoder, within the apparatus, compares high-order command bits provided on a serial bus with corresponding bits of recognized non-memory read commands. An early non-memory read command is asserted when incoming command bits match a non-memory read command. Early responsive data is prepared speculatively during the time the remainder of command bits is received and decoded. A determination of command speculation correctness is made after receipt of the full command. If the full command received is not the speculated non-memory read command, the prepared data is discarded. Earlier prepared data is produced as the subsystem response if the full command matches the speculative non-memory read command. For incoming commands with operands, such as an address, the same speculative determination based on high-order operand bits is performed.

Abstract: Disclosed is a pipelined motion estimation system and method. The pipelined motion estimation system includes a current frame input storage means for storing contents of a current frame and a previous frame input storage means for storing contents of one or more previous frames. A sum-of-absolute differences calculation module concurrently determines a best fit motion vector from a plurality of potential motion vectors where each of the plurality of potential motion vectors is based upon a pixel-based search pattern. A sum-of-absolute differences (SAD) logic block concurrently determines a minimum residual value from the plurality of motion vectors. The motion vector having the minimum residual value is used as a component in encoding video data.

Abstract: An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.

Abstract: A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to relaize said first delay altered by the fraction number of delay elements.

Abstract: A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder.

Abstract: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.

Abstract: Methods, systems, and apparatus, including computer program products for identifying optical disc media. In one aspect a method is provided that includes receiving printed information read from an optical media disc. Identifying a media-type of the optical media disc from the printed information. The printed information can be printed on optical media disc in ink. The printed information can be printed on optical media disc which includes a plurality of stripes.

Abstract: Quantum well charge trap transistors are disclosed featuring an ion implanted region below a stack of high-low-high bandgap materials arranged in a sandwich structure. Source and drain electrodes on either side of implanted region, as well as a control gate above the stack allow for electrical control. The implanted region, functioning to provide an offset to the threshold for conduction, is less than feature size F using a technique with spacer masks created for implantation, then removed. The quantum well charge trap stack is built in the area where the spacers were removed with a polysilicon gate atop the stack. Edges of the polysilicon gate are used for self-aligned placement of source and drain.

Abstract: Bit lines in a memory array are configured by a select switch matrix to apply the same VD voltage to two adjacent bit lines on the drain side of a selected memory cell for the purpose of blocking charge leakage through the cell adjacent to the selected or addressed cell. The switch matrix features transistors with electrodes connected to bit line segments while control electrodes are connected to control lines from a select decoder. The switch matrix communicates with address decoders for setting switches needed to configure the bit lines as needed with the charge leakage blocking voltage.

Abstract: A first mask set is used to define parallel active area stripes while a second mask set with memory cell stripes is perpendicular to the first mask set. The second mask set features cell masks with spaced apart branches, one for a non-volatile memory cell. The branch for the non-volatile memory cell has a mask portion for defining a subsurface charge region for communicating charge to a floating gate. The branches can use sub-masks for defining openings that are less than feature size, for example, for defining the subsurface charge region, yet allowing regions apart from spacers to define feature size and larger gates for desired channel lengths. The implantation of the charge region allows for self-aligned implanting of source-drain regions at locations that have been optimized for desired channel lengths or other parameters. By implanting source-drain regions late in the manufacturing process, there is no overlap with previously formed gates.

Abstract: A system for sensing the supply current of a switched DC-to-DC converter. The system includes a first circuit that senses a first voltage that is proportional to the supply current, wherein the first voltage has first ripple; a second circuit coupled to the first circuit, wherein the second circuit outputs a second voltage that is based on the first voltage, and wherein the second voltage has a second ripple that is smaller than the first ripple; and a third circuit coupled to the second circuit, wherein the third circuit compares the second voltage to a reference voltage to provide an indication of the supply current.

Abstract: An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

Abstract: Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate.

Abstract: Apparatus and a method for adding non-volatile memory cells with trench-filled vertical gates to conventional MOSFET surface devices that have their drain and source regions horizontally positioned near the top surface of a substrate. A surface MOSFET device is used as a structural platform to which is added a vertical trench-filled polysilicon gate and a word line region using a small number of additional mask layers and fabrication process modifications. A vertical trench filled polysilicon gate is formed in a deep trench in a lower region of the substrate and adjacent to a MOSFET body portion of the substrate. The vertical trench-filled polysilicon gate in the deep trench is isolated by dielectric material from the body portion of the MOSFET and from a word line region that is formed in the lower region of the substrate.