Abstract: A shift register includes a first voltage stabilizing unit, a second voltage stabilizing unit, a main pull-down unit and a main pull-up unit. The first voltage stabilizing unit is used to pull a first driving control signal to a low voltage terminal when a first stabilizing control signal is high. The second voltage stabilizing unit is used to pull the first driving control signal to the low voltage terminal when a second stabilizing control signal is high. The main pull-down unit includes a first sub-pull-down unit controlled by a second gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a first display mode, and a second sub-pull-down unit controlled by a third gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a second display mode. The main pull-up unit is used for pulling up a first gate-terminal signal.

Abstract: A method for fabricating a display panel includes forming a first patterned conductive layer, a gate insulation layer, a semiconductor channel layer, a first passivation layer, a second patterned conductive layer and a pixel electrode on a first substrate. The first patterned conductive layer includes a gate electrode, and the second patterned conductive layer includes a source electrode, a drain electrode and a data line. The patterns of the gate insulation layer, the first passivation layer and the second patterned conductive layer are defined by an etching process and a lift-off process with the same photomask.

Abstract: A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern.

Abstract: A display apparatus includes a pixel array, a data line and a data driver. The pixel array has adjacent first and second pixels disposed in different rows. The data line transmits first and second pixel voltages to be written into the first and second pixels respectively. The first and second pixel voltages are employed to illustrate a same frame. The data driver is utilized for generating the first and second pixel voltages furnished to the data line based on input image data. The data driver includes a voltage analysis unit and a voltage setting unit. The voltage analysis unit is used for calculating a voltage difference between the first and second pixel voltages, and for comparing the voltage difference with a preset value so as to generate a control signal. The voltage setting unit is utilized for setting the voltage of the data line according to the control signal.

Abstract: An organic light-emitting diode circuit and a driving method thereof are disclosed herein. The organic light-emitting diode circuit includes a storage unit, a transistor, a coupling capacitor, a compensation unit, an input unit, a switch unit, and an organic light-emitting diode. The transistor is configured to be driven by a voltage stored in the storage unit so that a second end of the transistor generates a driving current. The coupling capacitor changes a voltage of the second end of the transistor. The compensation unit changes the voltage level at the second end of the transistor according to a first scan signal. The input unit transmits a data voltage to the storage unit according to a second scan signal. The switch unit is turned on according to a light-emitting signal so that the driving current is transmitted to the organic light-emitting diode through the switch unit.

Abstract: A display device including a display panel, a first polarizer, a second polarizer, a first phase compensation film, and a second phase compensation film is provided. The first polarizer and the second polarizer are disposed on two sides of the display panel. The first polarizer has a first light-absorption axis, and the second polarizer has a second light-absorption axis. The first phase compensation film and the second phase compensation film are disposed between the first polarizer and the second polarizer. The second phase compensation film obeys a first formula: R ? ? ?1 ?1 > R ? ? ?2 ?2 > R ? ? ?3 ?3 , wherein R?1, R?2 and R?3 are horizontal phase retardation values of the second phase compensation film when wavelengths of lights passing through the second phase compensation film are respectively ?1, ?2 and ?3, and ?1<?2<?3.

Abstract: A liquid crystal panel has a display region and a peripheral region surrounding the display region. The liquid crystal panel includes a first substrate, a second substrate, a liquid crystal layer, a first alignment layer, a second alignment layer and at least one patterned water repellent layer. The first substrate is disposed opposite to the second substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. The first alignment layer is disposed on the first substrate, and the second alignment layer is disposed on the second substrate. The patterned water repellent layer is disposed on the first substrate and/or on the second substrate. The patterned water repellent layer is disposed in the peripheral region. A thickness of the patterned water repellent layer is less than or equal to a thickness of the first alignment layer or a thickness of the second alignment layer.

Abstract: An optical sensor circuit includes a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The capacitor includes a first terminal and a second terminal. Each transistor includes a first terminal, a control terminal, and a second terminal. The second terminal of the capacitor is coupled to a reference voltage terminal. The first terminals of the third transistor and the fourth transistor are coupled to a first voltage terminal. The second terminal of the fifth transistor is coupled to a readout line.

Abstract: A display device includes a substrate and subpixel groups disposed on the substrate. Each subpixel group includes four first subpixels for emitting four first color lights, four second subpixels for emitting four second color lights, and eight third subpixels for emitting eight third color lights. The first subpixels, the second subpixels, and the third subpixels are respectively arranged adjacent to each other along a first axis and a second axis intersecting the first axis, in which each of the first subpixels is located adjacent to another one of the first subpixels along the first axis or the second axis, each of the second subpixels is located adjacent to another one of the second subpixels along the first axis or the second axis, and each of the third subpixels is located adjacent to another one of the third subpixels along at least one of the first axis and the second axis.

Abstract: A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

Abstract: A touch display apparatus includes a touch driver and a display driver. The touch driver outputs touch signals to drive a touch panel. The display driver outputs scan signals to drive a display panel. A display driver has a plurality of shift registers, and each of the plurality of shift registers includes a pull-up unit, a driving unit, a pull-down unit and a holding unit. The pull-up unit is electrically connected to a driving node for outputting a driving voltage. The driving unit is electrically connected to the driving node for outputting a first scan signal according to a clock. A pull-down unit is electrically connected to the driving node and the output terminal, for pulling down the voltage level of the driving voltage and the first scan signal, respectively. The holding unit is electrically connected to the driving node.

Abstract: A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

Abstract: A clock generator circuit of a liquid display panel includes a charge sharing switch unit, a first capacitor, a first switch, a second switch, a third switch and a fourth switch. The charge sharing switch unit is configured to receive control signals and accordingly output a first-polarity voltage to the first capacitor. The clock generator circuit is configured to turn on the first switch, the second switch, the third switch and the fourth switch according to a specific sequence thereby outputting a clock signal. An operation method for the aforementioned clock generator circuit is also provided.

Abstract: A display panel includes a first substrate, first gate lines, first data lines, second data lines, third data lines, fourth data lines, first sub-pixels, second sub-pixels and first shielding electrodes. The first substrate has a plurality of first sub-pixel regions and second sub-pixel regions. The first gate lines extend along a first direction. The first data lines, the second data lines, the third data lines and the fourth data lines extend along a second direction and are sequentially arranged in the first direction. The first sub-pixel is electrically connected to one of the first data line and the second data line. The second sub-pixel is electrically connected to one of the third data line and the fourth data line. The first shielding electrodes extend along the second direction and are disposed in a common boundary between the first sub-pixel region and the second sub-pixel region adjacent to each other.

Abstract: An organic light-emitting display panel and a fabrication method thereof include using an inkjet printing process to form the organic emission material of the display panel and providing a specific design of the relative position of the spacer and the planarization layer with ink-repellent material such that the spacer can be effectively fixed on the array substrate without falling from the planarization layer.

Abstract: A display panel includes a first substrate structure, a second substrate structure and a non-self-luminous display medium layer. The first substrate structure includes a first substrate, a first common electrode, a pixel electrode and a first alignment film. The second substrate structure is disposed opposite to the first substrate structure. The second substrate structure includes a second substrate, a second common electrode and a second alignment film. The non-self-luminous display medium layer is interposed between the first alignment film and the second alignment film. A first capacitance is formed between the first common electrode and the pixel electrode, a second capacitance is formed between the pixel electrode and the second common electrode, and a ratio of the second capacitance to the first capacitance is substantially between 0.7 and 1.3.

Abstract: A liquid crystal display (LCD) has a pixel matrix, a plurality of shift registers, a plurality of common voltage generators, a plurality of common voltage buffers, and a plurality of primary bidirectional switch circuits. The shift registers sequentially output gate signals to scan lines of the pixel matrix. The common voltage generators output initial common voltages according to the gate signals. The common voltage buffers are configured to buffer the initial common voltages to output a plurality of common voltages to a plurality of common voltage lines of the pixel matrix. Each of the primary bidirectional switch circuits is configured to control electrical connection between two of the common voltage lines according to one or more gate signals outputted from at least one of the shift registers.

Abstract: A bright dot detection method adapted to be used in a display panel including a plurality of gate lines, a plurality of source lines and a bright dot detection module. The plurality of gate lines and the plurality of sources line are interlaced thereby forming a plurality of pixels. The bright dot detection method includes: driving the plurality of pixels through enabling the plurality of gate lines simultaneously, thereby forming a first bright line in a first direction; and driving the plurality of pixels through enabling the plurality of gate lines sequentially and providing a control signal to the bright dot detection module, thereby forming a second bright line in a second direction, wherein a bright dot is positioned where the first and second bright lines meet with each other. A display panel is also disclosed.