Abstract: A ball grid array (BGA) and via pattern includes a printed circuit board (PCB) having a surface on which a plurality of regions are formed and a transmit (TX) and receive (RX) cluster comprising a transmit differential signal pair and a receive differential signal pair formed using at least a portion of the plurality of regions on the surface of the PCB, the transmit differential signal pair and the receive differential signal pair comprising nodes arranged in a diagonal orientation in which each node of the receive differential signal pair is equidistant from each node of the transmit differential signal pair.

Abstract: A floor planning tool is provided that performs the functions that are typically performed by floor planning tools, but in addition, determines the supply of routing resources and the demand on routing resources for all routing channels while applying variable routing rules and static timing estimations to arrive at a preliminary routed floor plan. This drastically reduces the number of iterations that subsequently will need to be performed by the floor planning tool and by routing and static timing analysis tools to arrive at a final routed floor plan.

Abstract: In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

Abstract: A memory system with integrated memory built-in self-test (BIST) circuitry has one or more pipeline registers interposed between combinational logic elements. These combinational logic elements can include write data decoding logic, memory control signal decoding logic, address counter logic, address comparison logic, data comparison logic, and next state decoding logic. Features can be included that compensate for the delay inherent in the pipeline registers.

Abstract: A circuit includes a first circuit portion operable as a digital-to-analog converter (DAC) for generating a DAC common mode voltage signal (outp), a second circuit portion having a comparator for comparing the DAC common mode voltage (outp) against a received signal common mode voltage (vsumdc), the comparator providing a single bit output, and a single bit register configured to receive the single bit output of the comparator, the single bit output used to control a feedback circuit, the feedback circuit configured to control the DAC common mode voltage signal.

Abstract: A memory system is provided in which at least one DRAM chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The DRAM chip is connected to the interposer via a Wide I/O interface to enable the DRAM chip and the memory controller chip to communicate with each other via the Wide I/O interface. The memory controller chip has a SerDes interface for communicating with a SerDes interface of an integrated circuit (IC) chip of the memory system.

Abstract: A laminate interconnect structure includes a core material and at least one additional layer adjacent the core material, a first electrically conductive via formed in the core material, and a second electrically conductive via formed in the core material, coaxial with the first electrically conductive via and separated from the first electrically conductive via by a non-conductive material.

Abstract: Systems and methods for direct cooling of transceivers, including transceivers used in electrical and optical communications systems. An electrical system includes a transceiver module with a housing that contains a plurality of apertures to allow air flow into and out of the transceiver module. The transceiver includes an internal heat sink located within the housing of the transceiver module, where the internal heat sink is thermally coupled to at least one internal component of the transceiver module. The electrical system also includes a cage for receiving and electrically connecting to the transceiver module.

Abstract: A cache memory and a tag memory are included in a banked memory system and used to effectively enable parallel write and read operations on each clock cycle, even though the memory banks consist of single-port devices that are not inherently capable of parallel write and read operations.

Abstract: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column. The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.

Abstract: Systems and methods for distribution analysis of a stacked-die integrated circuit (IC) are described. The stacked-die integrated circuit includes a primary die, and clock load information for the primary die of the IC is determined. Additionally, a clock load model may be created using the clock load information for the primary die. Clock load information for a second die that is coupled to the primary die may also be determined. The clock load information for the second die may be incorporated into the clock load model to create an enhanced clock load model of the stacked-die IC, which may then be analyzed as if a single-die IC.

Abstract: A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design.

Abstract: A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Abstract: Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus are presented. The circuits and methods are responsive to an idle condition on the bidirectional bus. The control signal is applied to and changes an electrical characteristic within the receiver to generate a voltage offset. The voltage offset prevents unintended voltage transitions in the power supply of circuits coupled to the bidirectional bus from generating a signal transition on an output signal connection of the receiver.

Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

Abstract: A method for forming a solid immersion lens (SIL) includes generating a focused ion beam, and projecting the focused ion beam onto an optical medium at locations defined by a binary bitmap milling pattern, wherein the locations at which the focused ion beam impact a surface of the optical medium are randomized over successive raster scans of the surface of the optical medium to form at least a portion of a hemispherical structure in the optical medium.

Abstract: Systems and methods for distribution analysis of a stacked-die integrated circuit (IC) are described. The stacked-die integrated circuit includes a primary die, and clock load information for the primary die of the IC is determined. Additionally, a clock load model may be created using the clock load information for the primary die. Clock load information for a second die that is coupled to the primary die may also be determined. The clock load information for the second die may be incorporated into the clock load model to create an enhanced clock load model of the stacked-die IC, which may then be analyzed as if a single-die IC.

Abstract: An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information.

Abstract: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Abstract: A phase-locked loop (PLL) includes PLL loop circuitry, a frequency divider, and a phase-frequency detector (PFD) that can produce both high-gain output signals to operate the PLL in a high-gain mode and normal output signals to operate the PLL in a normal (not high-gain) mode. A mode signal can be used to switch the PFD between high-gain mode and normal operational mode. When the mode signal indicates high-gain mode, the PFD output signals are extended by one or more additional clock cycles beyond their length when the mode signal indicates normal operational mode.