Abstract: A gain control circuit, suitable for controlling the amplitude of a voltage-controlled oscillator, includes a duty cycle detector, an analog-to-digital converter, and a function generator. The gain control circuit provides a digitally enabled negative feedback loop. The duty cycle detector generates an estimate of the amplitude. The function generator receives a target amplitude as well as a digital representation of the estimate of the amplitude. The function generator calculates a modified estimate and periodically compares the same to the target value to generate a control word. The control word is arranged to enable current sources in the voltage-controlled oscillator.

Abstract: A method for protecting input/output (I/O) circuits on an integrated circuit (IC) from electrostatic discharge (ESD) is disclosed. The method includes the steps of providing at least one protective device on a surface of a first semiconductor die and applying a conductive shorting layer over a select region of the surface to electrically couple at least one metallic stud to the at least one protective device. After bonding the IC die to a second IC die and/or testing one or more core circuits, the conductive shorting layer is removed to enable high-speed I/O connections arranged in the select region of the semiconductor die. An IC assembly includes first and second semiconductor dice. One of the dice includes a protective device along a surface. An electrically conductive shorting layer couples the protective device to a conductive element that is further coupled to I/O circuit elements.

Abstract: A proximity sensor device is provided in compact unit that has the ability to sense or monitor in different directions, such as sensing or monitoring in both the vertical and horizontal directions. Methods are also provided. In an illustrative embodiment, the proximity sensor device includes a first transmitting/receiving pair and a second transmitting/receiving pair on a printed circuit board along with an IC to control the transmitters and receivers, as well as, in some embodiments, to provide signal filtering, amplification or other desired features.

Abstract: The present systems and methods extend the frequency range of a clock signal generated with a phase-locked loop (PLL). The PLL receives a reference signal from a reference signal divider and a feedback signal from a feedback signal divider. The PLL generates an output signal that is forwarded to a programmable divider. The programmable divider includes control logic, core logic, and post-processing logic. The control logic synchronizes signals distributed throughout the system to prevent metastability. The core logic generates a divide-by-N waveform that is forwarded to the post-processing logic. The post-processing logic generates a half duty cycle clock signal responsive to the divide-by-N waveform.

Abstract: An integrated circuit package comprises a package substrate, an application specific integrated circuit (ASIC) having a first area and formed on a first wafer made from a select semiconductor material, a second wafer of the select semiconductor material, and a supplemental-integrated circuit. The supplemental-integrated circuit has a second area different from the first area. The first wafer includes a through-wafer via to couple the ASIC to the package substrate. An active surface of the ASIC is coupled to the second wafer. The second wafer is arranged with a window there through that is sized to closely receive and align one or more bonding interfaces of the supplemental-integrated circuit to respective bonding interfaces of the ASIC. A corresponding method for assembling a die-stacked integrated circuit package is disclosed.

Abstract: A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design.

Abstract: A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft errors and soft error rates (SER) in storage elements on the ASIC. The interface device receives commands and data from the computer, translates the commands and data from a first protocol to a second protocol and communicates the commands and data in the second protocol to the ASIC. A method for measuring SER in the ASIC includes baseline, comparison, and latch up accesses of data in a scan chain in the ASIC. Between accesses, the ASIC is exposed to a neutron flux that accelerates the occurrence of soft errors due to ionizing radiation upon the ASIC.

Abstract: A system for accessing circuitry on a flip chip circuit device with active circuitry and full-thickness bulk silicon includes a moveable surface for supporting and locating the circuit device in a plane, an infrared (IR) imaging device located at a defined perpendicular distance from a surface of the bulk silicon, the surface of the bulk silicon parallel to the plane and a milling chamber configured to direct an etchant and a focused ion beam to the surface of the bulk silicon, resulting in a gas-enhanced milling process that creates a milled cavity in the bulk silicon. The system produces an IR reflective material located at a base of the cavity, wherein the circuit device is located within a field of view of the IR imaging device such that the IR reflective material is brought into focus by moving the IR imaging device an adjustable distance perpendicular to the surface of the bulk silicon, and where the adjustable perpendicular distance is indicative of a depth of the cavity.

Abstract: Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus are presented. The circuits and methods are responsive to an idle condition on the bidirectional bus. The control signal is applied to and changes an electrical characteristic within the receiver to generate a voltage offset. The voltage offset prevents unintended voltage transitions in the power supply of circuits coupled to the bidirectional bus from generating a signal transition on an output signal connection of the receiver.

Abstract: A tiered integrated circuit (IC) assembly includes stacks of a limited number of ICs coupled to each other and arranged in a first direction across a base tier and a second tier. The base tier includes ICs and a data bridge. Each of the ICs includes a respective array of through silicon vias (TSVs) arranged in parallel with the first direction. The data bridge includes submicron metal interconnects (densely spaced electrical conductors) arranged in a plane that is substantially orthogonal to the first direction. The second tier is adjacent to the base tier and includes respective high-performance ICs different from the ICs of the base tier. The TSVs provide power and ground paths to the ICs in the second tier. In an example embodiment, the ICs in the second tier support one or more data bridges for connecting adjacent stacks.

Abstract: A cache memory and a tag memory are included in a banked memory system and used to effectively enable parallel write and read operations on each clock cycle, even though the memory banks consist of single-port devices that are not inherently capable of parallel write and read operations.

Abstract: An integrated circuit package comprises a package substrate, an application specific integrated circuit (ASIC) having a first area and formed on a first wafer made from a select semiconductor material, a second wafer of the select semiconductor material, and a supplemental-integrated circuit. The supplemental-integrated circuit has a second area different from the first area. The first wafer includes a through-wafer via to couple the ASIC to the package substrate. An active surface of the ASIC is coupled to the second wafer. The second wafer is arranged with a window there through that is sized to closely receive and align one or more bonding interfaces of the supplemental-integrated circuit to respective bonding interfaces of the ASIC. A corresponding method for assembling a die-stacked integrated circuit package is disclosed.

Abstract: A configurable memory sheet includes a plurality of segmentable memory banks arranged on a repeating grid such that the plurality of segmentable memory banks can be configured for applications with a variety of circuit elements, where the plurality of segmentable memory banks are configured into memories by their connections to the variety of circuit elements.

Abstract: A programmable delay element with a variable delay generator employs feed forward and feedback control signals to corresponding feed forward and feedback control elements integrated within the variable delay generator. The variable delay generator is responsive to a control signal. The variable delay generator uses transfer switches to couple reactive circuit elements to a signal node in accordance with the control signal. The feed forward element couples a fixed voltage to corresponding nodes of the feed back element. The feedback element completes a bypass circuit to apply the fixed voltage to the signal node once the programmable delay element has delayed a source signal. The feed forward element is responsive to a buffered version of the source signal. The feedback element is responsive to a buffered version of the output of the delay element. A corresponding method for reducing frequency induced delay variation in a programmable delay element is disclosed.

Abstract: A phase generator includes a delay element configured to receive an input signal and delay the input signal by a predetermined amount to develop a delayed version of the input signal, a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal, a circuit configured to generate a reference signal, and a comparator configured to receive an output of the logic element and the reference signal. The comparator is configured to generate a control signal that is dependent on the difference between the output of the logic element and the reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal.

Abstract: A receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the receiver assembly. A bias signal directs the bridge circuit over a set of worst case conditions.

Abstract: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.

Abstract: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.

Abstract: The phase relationship between two clock signals in an integrated circuit (IC) is determined by transforming each of the clock signals into a data word, where bit transitions in the data word represent signal transitions in the clock signal, and comparing the two data words. For example, in an IC having a de-serializer as part of its input/output logic, the clocks are sequentially multiplexed into the de-serializer, which transforms the clocks into parallel-format data words. The resulting words corresponding to the first and second clock signals can then be compared to determine clock signal transition differences and thus the phase relationship between the corresponding clocks signals.