Patents Assigned to Avago Technologies International Sale Pte. Limited
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Patent number: 10223322Abstract: Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing non-standard bus information.Type: GrantFiled: April 18, 2016Date of Patent: March 5, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Mohammad Mobin, Anup Tirumala, Haitao Xia
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Patent number: 10225108Abstract: A device implementing a channel estimation for multi-channel transmissions system may include at least one processor configured to receive a set of signals over a set of channels, wherein each signal of the set of signals includes one of a set of channel estimation sequences. The set of channel estimation sequences may have been selected based at least in part on a signal quality metric, such as a peak-to-average power ratio, associated with a combination of the set of signals. The at least one processor may be further configured to perform a channel estimation for each channel based at least in part on the channel estimation sequence included in the signal received over each channel. In one or more implementations, the set of channel estimation sequences may be selected to minimize the signal quality metric associated with the combination of the plurality of channels.Type: GrantFiled: December 8, 2016Date of Patent: March 5, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Avraham Kliger, Leo Montreuil
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Patent number: 10223009Abstract: A system and method for efficient cache buffering are provided. The disclosed method includes receiving an Input/Output (I/O) command from a host system at a storage controller, parsing the I/O command at the storage controller with a host I/O manager to extract command instructions therefrom. The host I/O manager is able to generate at least one local message that includes the command instructions extracted from the I/O command and transmit the at least one local message to a cache manager. The cache manager is enabled to work in local memory to execute the command instructions contained in the at least one message. The cache manager is also configured to chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system.Type: GrantFiled: October 26, 2016Date of Patent: March 5, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Horia Simionescu, Timothy Hoglund, Sridhar Rao Veerla, Panthini Pandit, Gowrisankar Radhakrishnan
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Patent number: 10222236Abstract: The present disclosure relates to an absolute position sensor. In one example, the absolute position sensor includes a Wiegand module and a control electronic that enable the absolute position sensor to operate in either a non-autonomous mode or an autonomous mode. In the autonomous mode there is no external energy available and a position sensor is supplied with energy by the Wiegand module.Type: GrantFiled: September 28, 2016Date of Patent: March 5, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Walter Mehnert, Thomas Theil
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Patent number: 10224450Abstract: A semiconductor device, silicon photomultiplier, and sensor are described. The disclosed semiconductor device is disclosed to include a substrate, a photosensitive area provided on the substrate, the photosensitive area corresponding to an area in which an electrical signal is generated in response to light impacting the photosensitive area, at least one trench substantially surrounding the photosensitive area, the at least one trench extending at least partially into the substrate, and a resistor confined by the at least one trench and in electrical communication with the active area such that the resistor is configured to carry electrical signals generated by the photosensitive area to a metal contact.Type: GrantFiled: June 27, 2017Date of Patent: March 5, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Claudio Piemonte, Alberto Giacomo Gola, Giovanni Paternoster, Fabio Acerbi
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Patent number: 10223314Abstract: A host connected to a switch using a PCI Express (PCIe) link. At the switch, the packets are received and routed as appropriate and provided to a conventional switch network port for egress. The conventional networking hardware on the host is substantially moved to the port at the switch, with various software portions retained as a driver on the host. This saves cost and space and reduces latency significantly. As networking protocols have multiple threads or flows, these flows can correlate to PCIe queues, easing QoS handling. The data provided over the PCIe link is essentially just the payload of the packet, so sending the packet from the switch as a different protocol just requires doing the protocol specific wrapping. In some embodiments, this use of different protocols can be done dynamically, allowing the bandwidth of the PCIe link to be shared between various protocols.Type: GrantFiled: August 16, 2016Date of Patent: March 5, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Badrinath Kollu
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Patent number: 10223020Abstract: A Ternary Content-Addressable Memory (TCAM) system is disclosed. In the system, writes to the memory are performed over several cycles. In order to ensure full visibility of all entries within the TCAM, a cache memory is provided. At the start of the TCAM write, the cache is written with the contents of the new entry. The cache entry is activated for the period of time that the corresponding entry in the TCAM is deactivated for rewriting. For each input value provided to the system, both the TCAM and the cache are checked for potential matches. The results of these checks are compared at output. In this manner, all entries within the TCAM can maintain full visibility even throughout a write period.Type: GrantFiled: November 24, 2015Date of Patent: March 5, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Publication number: 20190068353Abstract: A system and method perform fine ranging on a plurality of cable modems in a network and distribute results. A CMTS grants access to a full duplex ranging probe to the plurality of cable modems, and probe results are distributed to the plurality of cable modems. A receive modulation error ratio (RxMER) uploaded from respective of the plurality of cable modems, and the CMTS identifies an interference group (IG) and bits/symbol for the plurality of cable moderns in a given sub-band. Full duplex operation is then performed in the given sub-band with known IG and bits/symbol.Type: ApplicationFiled: May 8, 2018Publication date: February 28, 2019Applicant: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Thomas J. KOLZE, Avi KLIGER
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Patent number: 10218498Abstract: The present disclosure is directed to a system and method for compressing keys of key-data item pairs for storage in a hash table to reduce power and/or area requirements of the memory used to implement the hash table. The system and method of the present disclosure use the hash function to compress a key of a key-data item pair. More specifically, the system and method of the present disclosure effectively remove information from the key that can be predicted using in the hash value of the key to generate a compressed key. Information in the key that is not predictable using the hash value of the key can be included in the compressed key to allow for recovery of the key.Type: GrantFiled: August 6, 2015Date of Patent: February 26, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventor: Abhay Kulkarni
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Patent number: 10218332Abstract: A matching circuit provides broadband impedance matching of first and second devices for processing RF signals in a broadband frequency range, the first device being inherently capacitive. The matching circuit includes a shunt inductor that transforms impedance of the first device to matching impedance at a matching resonance frequency in a middle portion of the broadband frequency range, and a series resonance circuit that has a series resonance frequency approximately the same as the matching resonance frequency. The series resonance circuit includes an inductor and a capacitor connected in series to the first device, and further transforms the matching impedance of the first device and the shunt inductor to a design matching impedance corresponding to the broadband frequency range. One end of the shunt inductor is connected to the first device, between the series resonance circuit and the first device or to an opposite side of the first device.Type: GrantFiled: October 30, 2015Date of Patent: February 26, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Martin Fritz, Hongya Xu, Usman Javaid, Jonathan Bamford
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Patent number: 10218225Abstract: A device and circuits are provided for wireless power transfer (WPT) gate-drive power reduction. A WPT receiver circuit includes a receive coil to couple to a transmit coil of a WPT transmitter circuit. A rectification circuit is coupled to the receive coil to generate a rectified voltage. The rectification circuit is a bridge rectifier circuit including a first set of field-effect transistors (FETs). One or more gate-drive control circuits improve power dissipation of the rectification circuit by controlling drive voltages of gate terminals of the first set of FET switches after start-up of the WPT receiver circuit.Type: GrantFiled: August 10, 2016Date of Patent: February 26, 2019Assignee: Avago Technologies International Sales PTE, LimitedInventor: Ryan Michael Desrosiers
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Patent number: 10218990Abstract: In some aspects, the disclosure is directed to methods and systems for encoding and sharing media clips via a social networking provider responsive to a user interaction via a single “like” or “share” button. Media may be constantly buffered as the user watches the program, such that the user need not initiate recording, enabling the user to quickly share amusing or media clips as they happen live. The device may decode, scale or subsample, and compress or re-encode the media to take up less space in a buffer of the device and/or to comply with copyright fair use requirements. Responsive to the user interaction or “share” command, the device may transfer the contents of the buffer to a social media service along with instructions to generate a post to the social network identifying the user, media, and/or buffer contents.Type: GrantFiled: January 24, 2017Date of Patent: February 26, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventor: Darren Neuman
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Patent number: 10216567Abstract: Various aspects of systems for generating parity bits for encoding based on a portion of a generator matrix are disclosed. In one aspect, a generator matrix includes a sub-block including a first set of elements circularly shifted from an identity matrix by a first amount, and a second set of elements circularly shifted from the identity matrix by a second amount. Bit permutation circuitry generates first bits according to input bits and the first amount. Each of the first bits is provided as input to a corresponding XOR device of XOR devices. Each of a set of storage registers stores an output of the corresponding XOR device. The bit permutation circuitry generates second bits according to the input bits and the second amount. The XOR devices perform bit-wise XOR operations on the stored outputs and the generated second bits, to provide a portion of the parity bits.Type: GrantFiled: August 22, 2018Date of Patent: February 26, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventor: Andrew Blanksby
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Patent number: 10216688Abstract: Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing transfer margin information.Type: GrantFiled: May 27, 2016Date of Patent: February 26, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Mohammad Mobin, Shaohua Yang, John Jansen, Haitao Xia
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Patent number: 10210105Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.Type: GrantFiled: December 17, 2015Date of Patent: February 19, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: James B. Williams, Shawn Adam Clayton, Maria Clara Gutierrez, Alexander Nicolson, IV, James Winston Smart, John Leland Wood, David James Duckman, Carl John Lindeborg, William Irving Leavitt
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Patent number: 10209992Abstract: A method and system for branch prediction are provided herein. The method includes executing a program, wherein the program comprising multiple procedures, and setting bits in a taken branch history register to indicate whether a branch is taken or not taken during execution of instructions in the program. The method further includes the steps of calling a procedure in the program and overwriting, responsive to calling the procedure, the contents of the taken branch history register to a start address for the procedure.Type: GrantFiled: October 31, 2014Date of Patent: February 19, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Sophie Wilson, Geoffrey Barrett
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Patent number: 10211281Abstract: In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device comprising a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further comprises an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.Type: GrantFiled: April 8, 2015Date of Patent: February 19, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Qian Tao, Fun Kok Chow
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Patent number: 10211881Abstract: Systems and methods for implementing an Energy-Efficient Ethernet (EEE) communication are provided. In some aspects, a method includes identifying an EEE signal configured to be communicated via a first set of wires. The method also includes processing the EEE signal such that the processed EEE signal is configured to be communicated via a second set of wires. The second set of wires including fewer wires than the first set of wires. The method also includes communicating the processed EEE signal via the second set of wires.Type: GrantFiled: August 9, 2013Date of Patent: February 19, 2019Assignee: Avago Technologies International Sales PTE. LimitedInventors: Peiqing Wang, Linghsiao Wang, Mehmet Vakif Tazebay
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Patent number: 10204006Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.Type: GrantFiled: October 28, 2015Date of Patent: February 12, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Zhijun Zhao, Shaohua Yang
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Patent number: 10203400Abstract: An optical measurement system is provided for performing time-of-flight distance measurement with ambient light suppression. The system has a detector circuit that includes a photodetector and an additional current gain element that amplifies the photocurrent produced by the photodetector. Placement of the additional current gain element near the photodetector allows low-power optical signals to be detected without amplifying noise from sources of the system that are outside of the detector circuit, thereby allowing a high signal-to-noise ratio to be achieved. Embodiments of the system include circuitry that automatically regulates the bias voltage of the photodetector to compensate for temperature and for fabrication process variations.Type: GrantFiled: April 29, 2016Date of Patent: February 12, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Milos Davidovic, Reinhard Enne, Gunther Steinle, Wolfgang Gaberl