Patents Assigned to Avago Technologies International Sales Pte. Limited
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Patent number: 11606311Abstract: A system for determining the servicing needs of a vehicle. In various embodiments, the system includes a remote server and a vehicle control module of the vehicle. The vehicle control module includes a first communication interface to enable communications with at least one vehicle device via a network fabric of the vehicle. The vehicle control module is configured to receive status data, from the vehicle device, relating to a performance status or operational status of the vehicle. The vehicle control module further includes a second communication interface that enables wireless communications with the remote server. The wireless communications include sending status data to the remote server. The remote server is configured to receive and interpret the status data to determine if the vehicle requires service, and send a response to the vehicle. When service is required, the response may cause the vehicle to provide a service indication.Type: GrantFiled: August 20, 2020Date of Patent: March 14, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventors: Nariman Yousefi, Yongbum Kim, John Walley, Sherman (Xuemin) Chen, Wael William Diab, Nicholas Ilyadis
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Patent number: 11601942Abstract: A device implementing unified coordination of wireless communications over multiple physical layers may include a MAC module communicatively coupled to first and second physical layer modules that are each configured to communicate with another device over first and second physical wireless channels, respectively. The MAC module may be configured to provide data to the first physical layer module for transmission to the another device over the first physical wireless channel, where the first physical wireless channel is associated with a first link parameter. The MAC module may be further configured to facilitate initializing the second physical wireless channel based at least in part on the first link parameter of the first physical wireless channel, and after initialization of the second physical wireless channel, provide second data to the second physical layer module for transmission to the another device over the second physical wireless channel.Type: GrantFiled: January 22, 2021Date of Patent: March 7, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventors: Vinko Erceg, Mark Gonikberg, Rohit Gaikwad, Hongyu Xie, Anand Iyer, Venkat Kodavati, Tirdad Sowlati, Payam Torab Jahromi, Matthew J. Fischer
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Patent number: 11595673Abstract: In some aspects, the disclosure is directed to methods and systems for reducing memory utilization and increasing efficiency during affine merge mode for versatile video coding by utilizing motion vectors stored in a motion data line buffer for a prediction unit of a second coding tree unit neighboring a first coding tree unit to derive control point motion vectors for the first coding tree unit.Type: GrantFiled: August 27, 2020Date of Patent: February 28, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventor: Minhua Zhou
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Publication number: 20230056730Abstract: Systems and methods transfer video data to an image processing system from a video source. Pixel data is received in a local buffer of a network interface controller and provided in a video transport packet. The video transport packet includes the pixel data, a media access control header and a video header. The video transport packet is received by another network interface controller that provides the pixel data directly into a video frame buffer of the image processing system.Type: ApplicationFiled: November 2, 2022Publication date: February 23, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventor: Dmitrii Loukianov
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Patent number: 11586580Abstract: A parallel processor system for machine learning includes an arithmetic unit (ALU) array including several ALUs and a controller to provide instructions for the ALUs. The system further includes a direct-access memory (DMA) block containing multiple DMA engines to access an external memory to retrieve data. An input-stream buffer decouples the DMA block from the ALU array and provides aligning and reordering of the retrieved data. The DMA engines operate in parallel and include rasterization logic capable of performing a three-dimensional (3-D) rasterization.Type: GrantFiled: July 8, 2021Date of Patent: February 21, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Friederich Jean-Baptiste Mombers
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Patent number: 11581853Abstract: A filter device configured to directly connect to a differential power amplifier of a transmit chain circuit. The filter device may include a transformer and a filter configured as a half lattice equivalent topology and having a single-ended output. The filter may be a lattice filter configured as a full lattice topology or a lattice equivalent filter configured as a half lattice equivalent topology. The filter includes a first branch having a first impedance network of one or more first impedance elements and a second branch having a second impedance network of one or more second impedance elements. The single-ended output of the filter device may connect to an antenna switch that is in turn connected to an antenna.Type: GrantFiled: January 27, 2021Date of Patent: February 14, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Sean Thomas Hansen, Jeesu Kim
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Patent number: 11582322Abstract: An apparatus and method for providing ML processing for one or more ML applications operating on one or more Internet of Things (IoT) devices includes receiving a ML request from an IoT device. The ML request can be generated by a ML application operating on the IoT device and include input data collected by the first ML application. A ML model to perform ML processing of the input data included in the ML request is identified and provided to an ML core for ML processing along with the input data included in the first ML request. The ML core produces ML processing output data based on ML processing by the ML core of input data included in the ML request using the ML model. The ML processing output data can be transmitted to the IoT device.Type: GrantFiled: October 31, 2019Date of Patent: February 14, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Prashant Katre, Yong Li, Fabian Russo, Darren Tokushige, Craig Arlen Detrick, Gary Jacob Skerl, Xuemin Chen
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Publication number: 20230037292Abstract: Methods and systems for early identification of bitrates for segments in adaptive bitrate streaming can allow the server to begin processing or transcoding content as necessary for delivery, reducing processing and transmission latency. In a first aspect, a client may request a second segment before the first segment has been completely received. The server may begin any transcoding processes for preparing the second segment, and once the server has completed sending the first segment, the server may begin transmitting the now-prepared or partially prepared second segment. The server can then transmit the first and second segment contiguously, with essentially no network dead time. In a second aspect, the client may transmit an early notification of parameters for the request of the second segment, allowing the server to begin transcoding. The client may subsequently request the already-prepared or partially prepared second segment, similarly reducing request-response processing latency.Type: ApplicationFiled: October 24, 2022Publication date: February 9, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventor: Alexander Garland MacInnis
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Patent number: 11575457Abstract: A method for power-smart packet processing includes, in response to an event trigger signal, generating, by a state machine, a number of enable signals. The method further includes applying the enable signals to a number of single-level inferred clock (SLICK) gates to generate multiple clock signals with cycles of latency. The clock signals are applied to at least some of a number of groups of flops used for packet processing. The enable signals are clock-gated enable signals that start at consecutive cycles of a main clock, and stay active for at least one cycle of the main clock. The method further includes using flow-aware clock-gating technology (FACT) to distinctly identify logic and tables and continually variable traffic (CVT) to control packet rate and packet spacing.Type: GrantFiled: January 19, 2021Date of Patent: February 7, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Sachin Prabhakarrao Kadu
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Publication number: 20230030497Abstract: A method for managing network traffic is shown. The method includes establishing a virtual tunnel between a source endpoint and a destination endpoint, the virtual tunnel including a plurality of data flow paths, each of the plurality of data flow streams connecting the source endpoint and the destination endpoint. The method includes providing, via the destination endpoint, a plurality of credits to the source endpoint, the plurality of credits provided via two or more of the plurality of data flow paths. The method includes updating, at the source endpoint, a data transmission sequence based on the received plurality of credits. The method includes providing a plurality of data packets based on the data transmission sequence to the destination endpoint.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventors: Vahid Tabatabaee, Niranjan Vaidya, Chih-Yuan Chang, Mark David Griswold
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Publication number: 20230034217Abstract: An integrated circuit (IC) package includes a one or more die, a package substrate, a thermal interface material, and a cover. The cover is disposed over or above the one or more die. The thermal interface material includes a surface modified metal and a silicon monomer.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventors: Mayank Mayukh, Shrikara Prabhu Tendel, Sam Karikalan, Nicole A. Butel
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Publication number: 20230036715Abstract: A method of reducing bias in multicast replication, the method comprising receiving a packet at a network device and determining a multicast group from the packet. The method further includes obtaining at least two or more destinations corresponding to the multicast group, replicating the packet for the at least two or more destinations, and forwarding the replicated packet to the at least two or more destinations in a randomized sequence.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventor: Santanu Sinha
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Patent number: 11569830Abstract: A system includes a digital-to-analog converter comprising a plurality of unit elements, and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes a circuit configured to determine a number of unit elements of a digital-to-analog converter to be transitioned (Ntm), determine a first number of unit elements to be turned on, and determine a second number of unit elements to be turned off. The circuit may further generate a first signal identifying individual unit elements of one or more unit elements of the digital-to-analog converter in the off state to be turned on, and a second signal identifying the individual unit elements of one or more unit elements of the digital-to-analog converter in the on state to be turned off.Type: GrantFiled: January 31, 2022Date of Patent: January 31, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Ahmed Elkholy, Adesh Garg
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Patent number: 11569804Abstract: An apparatus includes control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic is configured to obtain a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, and adjust a delay of the reference signal until the second phase matches the first phase. The control logic is further configured to measure a total delay of the reference signal when the second phase matches the first phase, and determine integral non-linearity of the phase interpolator at the first code based on the total delay. The control logic may further calibrate a first code of a phase interpolator based, at least in part, on the integral non-linearity.Type: GrantFiled: April 22, 2022Date of Patent: January 31, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventors: Seong-Ho Lee, SangHye Chung, Hyung-Joon Jeon, Vadim Milirud, Wei Zhang, Angus Tang
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Publication number: 20230013148Abstract: A system for controlling power distribution within a vehicular communication network, including a power source equipment comprising a first port in communication with a network node module of a device, and a Power over Ethernet (POE) management module. The POE management module is configured to enable POE to the device via the first port, monitor a current draw of the device, determine whether the current draw of the device exceeds a threshold, and disable POE to the device, responsive to determining that the current draw exceeds the threshold.Type: ApplicationFiled: September 20, 2022Publication date: January 19, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventors: Nariman YOUSEFI, Yongbum KIM, John WALLEY, Xeumin CHEN, Wael W. DIAB, Nicholas ILYADIS
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Patent number: 11558289Abstract: The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.Type: GrantFiled: October 22, 2021Date of Patent: January 17, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Sachin Prabhakarrao Kadu
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Publication number: 20230010078Abstract: Systems, methods and apparatus for processing video can include a processor. The processor can be configured to perform object detection to detect visual indications of potential objects of interest in a video scene, to receive a selection of an object of interest from the potential objects of interest, and to provide enhanced video content within the video scene for the object of interest indicated by the selection.Type: ApplicationFiled: July 12, 2021Publication date: January 12, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventors: Zhijie Yang, Xuemin Chen
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Patent number: 11552906Abstract: A network where FC and Ethernet storage traffic share the underlying network. The network extends FC SAN storage specific attributes to Ethernet storage devices. The network is preferably formed of FC switches, so each edge switch acts as an FCoE FCF, with internal communications done using FC. IP packets are encapsulated in FC packets for transport. Preferably, either each outward facing switch port can be configured as an Ethernet or FC port, so devices can be connected as desired. FCoE devices connected to the network are in particular virtual LANs (VLANs). The name server database is extended to include VLAN information for the device and the zoning database has automatic FCOE_VLAN zones added to provide a mechanism for enhanced soft and hard zoning. Zoning is performed with the conventional zoning restrictions enhanced by including the factor that any FCoE devices must be in the same VLAN.Type: GrantFiled: June 24, 2019Date of Patent: January 10, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Jesse Willeke, Kiran Sangappa Shirol, Chandra Mohan Konchada
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Patent number: 11544354Abstract: A system and method are disclosed for provisioning IP features in a system-on-chip. A plurality of identical chips are fabricated, each of which is capable of have a number of features enabled or disabled. As a default, all features are disabled. A production process is later carried out, in which the chip is installed in a greater device. During this process, the manufacturer requests a license the IP owner for enablement of various features. Using secure communications, a license is granted identifying the features to be enabled, and a volume of units permitted to be manufactured. The license information is encrypted using a key already known to the chip, and sent to the manufacturer. The chip receives the license information during provisioning, extracts relevant provisioning information using the key, and a secure processing system provisions the relevant features. Log information is generated to allow the IP owner to verify license compliance.Type: GrantFiled: March 7, 2018Date of Patent: January 3, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventors: Yong Li, Sherman (Xuemin) Chen, Abbas Saadat, Fabian Russo, Dexter Bayani, Brett Tischler, Bryant Tan
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Patent number: 11528412Abstract: An apparatus for stitching together multiple camera images to form a blended image having an output projection format. The apparatus is configured to convert each of the multiple camera images into the output projection format. It is configured to stitch together the converted images to form a single image. It is also configured to output the single image as the blended image having the output projection format.Type: GrantFiled: June 21, 2018Date of Patent: December 13, 2022Assignee: Avago Technologies International Sales Pte. LimitedInventors: James Andrew Hutchinson, Thomas Oscar Miller, Stephen John Barlow, Jack Stuart Haughton