Patents Assigned to Avalanche Technology, Inc.
  • Patent number: 11417836
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure incorporating three magnetic free layers separated by two perpendicular enhancement layers (PELs) and having a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a third perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.
    Type: Grant
    Filed: January 23, 2021
    Date of Patent: August 16, 2022
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Zihui Wang
  • Patent number: 11348971
    Abstract: The present invention is directed to a perpendicular magnetic structure comprising a first seed layer including tantalum, a second seed layer deposited on top of the first seed layer and including iridium, a third seed layer deposited on top of the second seed layer, and a fourth seed layer deposited on top of the third seed layer and including chromium. The third seed layer includes one of NiFe, NiFeB, NiFeCr, CoFeB, CoFeTa, CoFeW, CoFeMo, CoFeTaB, CoFeWB, or CoFeMoB. The perpendicular magnetic structure further includes a magnetic fixed layer structure formed on top of the fourth seed layer and having an invariable magnetization direction substantially perpendicular to a layer plane of the magnetic fixed layer structure. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The magnetic material includes cobalt. The transition metal includes one of nickel, platinum, palladium, or iridium.
    Type: Grant
    Filed: February 13, 2021
    Date of Patent: May 31, 2022
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 11289142
    Abstract: The present invention is directed to a nonvolatile memory device including a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes a first input node through which a reference current passes; a second input node through which a read current from the memory sectors passes; a sense amplifier configured to compare input voltages and having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a variable current source connected to the reference resistor at one end and ground at the other end; and a second current source connected to the second input node at one end and ground at the other end.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 29, 2022
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Ebrahim Abedifard
  • Patent number: 11211107
    Abstract: The present invention is directed to a nonvolatile memory device that includes a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a first target resistor and a balancing resistor connected in series between the first input node and the first input terminal; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a second target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: December 28, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Ebrahim Abedifard
  • Patent number: 11127787
    Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes at least one conductor layer interleaved with insulating layers.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 21, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Bing K. Yen, Jing Zhang
  • Patent number: 11127782
    Abstract: The present invention is directed to a memory cell array comprising an array of magnetic memory elements arranged in rows and columns; a plurality of electrodes, each of which is formed adjacent to a respective one of the array of magnetic memory elements; a plurality of first conductive lines, each of which is connected to a respective row of the array of magnetic memory elements along a row direction; and a plurality of composite lines. Each composite line includes a volatile switching layer connected to a respective column of the plurality of electrodes along a column direction; an electrode layer formed adjacent to the volatile switching layer; and a second conductive line formed adjacent to the electrode layer. The dimension of the volatile switching layer may be substantially larger than the size of the magnetic memory element along the row direction.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 21, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Bing K. Yen
  • Patent number: 10950659
    Abstract: The present invention is directed to a perpendicular magnetic structure including a first seed layer comprising a first transition metal and nitrogen, a second seed layer deposited on top of the first seed layer, and a third seed layer deposited on top of the second seed layer. One of the second and third seed layers comprises cobalt, iron, and boron. The other one of the second and third seed layers comprises chromium. The perpendicular magnetic structure further includes a magnetic fixed layer structure formed on top of the third seed layer and having an invariable magnetization direction substantially perpendicular to a layer plane of the magnetic fixed layer structure. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a second transition metal. The first transition metal is titanium or tantalum. The second transition metal is one of nickel, platinum, palladium, or iridium.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 16, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 10936327
    Abstract: The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; directly executing an operating system software from an external MRAM by the SoC without loading the operating system into a volatile memory; and directly executing an application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for storing the operating system software and the application software.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 2, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Ngon Van Le, Ravishankar Tadepalli
  • Patent number: 10910555
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure incorporating three magnetic free layers separated by two perpendicular enhancement layers (PELs) and having a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a third perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: February 2, 2021
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Xiaojie Hao, Longqian Hu, Yiming Huai
  • Patent number: 10838623
    Abstract: A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 10832751
    Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Dean K. Nobunaga, Ebrahim Abedifard
  • Patent number: 10818731
    Abstract: The present invention is directed to a memory array including one or more memory layers, each of which includes a first plurality of memory cells and a second plurality of memory cells arranged in alternated odd and even columns, respectively; multiple odd horizontal lines with each connected to a respective odd column of the first plurality of memory cells; multiple even horizontal lines with each connected to a respective even column of the second plurality of memory cells; multiple transverse lines with each connected to one of the first plurality of memory cells and a respective one of the second plurality of memory cells disposed adjacent thereto along a row direction; and multiple vertical lines with each connected to a respective one of the multiple transverse lines. The odd horizontal lines collectively form fingers of a first comb structure and the even horizontal lines collectively form fingers of a second comb structure.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 27, 2020
    Assignee: Avalanche Technology, Inc.
    Inventor: Kimihiro Satoh
  • Patent number: 10818330
    Abstract: The present invention is directed a method for programming multiple memory cells connected to a common word line to different resistance regimes. Each cell includes a bipolar switching memory element and an access transistor coupled in series between first and second conductive lines. The memory element and access transistor are disposed adjacent to the first and second conductive lines, respectively. The method includes the steps of applying a first voltage to the common word line to program a first group of memory cells to a first resistance regime; and after the first group of memory cells is programmed to the first resistance regime, programming a second group of memory cells to a second resistance regime by raising the potential of second conductive lines connected to the first group of memory cells to a second voltage and raising the first voltage of the common word line to a third voltage.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 27, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Thinh Tran, Mourad El Baraji
  • Patent number: 10811072
    Abstract: The present invention is directed to a method for programming a memory cell that includes a transistor and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Parviz Keshtbod, Ebrahim Abedifard
  • Patent number: 10727400
    Abstract: The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; a non-magnetic metal layer formed adjacent to the magnetic free layer structure; an oxide layer formed adjacent to the non-magnetic metal layer; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure opposite the non-magnetic metal layer; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer; a second magnetic reference layer separated from the first magnetic reference layer by a perpendicular enhancement layer; an antiferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the antiferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai, Huadong Gan, Yuchen Zhou
  • Patent number: 10720469
    Abstract: The present invention is directed to a magnetic structure including a first seed layer, a second seed layer formed on top of the first seed layer, and a third seed layer made of chromium or iridium formed on top of the second seed layer. One of the first and second seed layers comprises cobalt, iron, and boron. The other one of the first and second seed layers is made of iridium, rhodium, cobalt, platinum, palladium, nickel, ruthenium, or rhenium. The magnetic structure further includes a magnetic fixed layer structure formed on top of the third seed layer and having an invariable magnetization direction substantially perpendicular to a layer plane thereof. The magnetic fixed layer structure includes layers of a magnetic material interleaved with layers of a transition metal. The transition metal may be nickel, platinum, palladium, or iridium.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: July 21, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Zihui Wang, Yiming Huai
  • Patent number: 10628169
    Abstract: The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; storing an operating system (OS) software and an application software on an external MRAM; directly executing the operating system software from the external MRAM by the SoC without loading the operating system into a volatile memory; directly executing the application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for permanently storing the operating system software and the application software.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 21, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Ngon Van Le, Ravishankar Tadepalli
  • Patent number: 10593727
    Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes a plurality of metal-rich particles or clusters embedded in a matrix or at least one conductor layer interleaved with insulating layers.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 17, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Bing K. Yen, Jing Zhang
  • Patent number: 10559624
    Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element, which has a low resistance state and a high resistance state, and a two-terminal selector coupled to the MTJ memory element in series. The MTJ memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween. The two-terminal selector has an insulative state and a conductive state. The two-terminal selector in the conductive state has substantially lower resistance when switching the MTJ memory element from the low to high resistance state than from the high to low resistance state. The voltages applied to the memory cell to respectively switch the MTJ memory element from the low to high resistance state and from the high to low resistance state may be substantially same.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 11, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Xiaojie Hao, Jing Zhang, Xiaobin Wang, Bing K. Yen
  • Patent number: RE47975
    Abstract: An STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer, causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 5, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Jing Zhang, Yiming Huai, Rajiv Yadav Ranjan, Yuchen Zhou, Zihui Wang, Xiaojie Hao