Patents Assigned to Avalanche Technology, Inc.
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Patent number: 9812499Abstract: The present invention is directed to a memory device including a memory cell coupled to two wiring lines at two ends thereof. The memory cell includes a memory element, which includes a magnetic free layer and a magnetic reference layer with a tunnel junction layer interposed therebetween, and a bi-directional two-terminal selector element having multiple threshold voltages coupled to the memory element in series. The magnetic free layer has a variable magnetization direction substantially perpendicular to a layer plane thereof and the magnetic reference layer has a fixed magnetization direction substantially perpendicular to a layer plane thereof. In an embodiment, the bi-directional two-terminal selector element includes two selector devices with each selector device including two electrodes with a switching layer interposed therebetween. In another embodiment, the bi-directional two-terminal selector element includes a selector device incorporating therein two switching layers.Type: GrantFiled: July 27, 2016Date of Patent: November 7, 2017Assignee: Avalanche Technology, Inc.Inventors: Kimihiro Satoh, Hongxin Yang
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Patent number: 9792047Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs.Type: GrantFiled: January 12, 2015Date of Patent: October 17, 2017Assignee: Avalanche Technology, Inc.Inventors: Mehdi Asnaashari, Siamack Nemazie
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Patent number: 9793003Abstract: A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.Type: GrantFiled: September 14, 2016Date of Patent: October 17, 2017Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Uday Chandrasekhar, Rajiv Yadav Ranjan, Yiming Huai
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Patent number: 9793319Abstract: The present invention is directed to a magnetic random access memory element that includes a multilayered seed structure formed by interleaving multiple layers of a first transition metal with multiple layers of a second transition metal; and a first magnetic layer formed on top of the multilayered seed structure. The first magnetic layer has a multilayer structure formed by interleaving layers of the first transition metal with layers of a magnetic material and has a first fixed magnetization direction substantially perpendicular to a layer plane thereof. The first transition metal is platinum or palladium, while the second transition metal is selected from the group consisting of tantalum, titanium, zirconium, hafnium, vanadium, niobium, chromium, molybdenum, and tungsten.Type: GrantFiled: October 17, 2016Date of Patent: October 17, 2017Assignee: Avalanche Technology, Inc.Inventors: Huadong Gan, Yiming Huai, Bing K. Yen, Roger K. Malmhall, Yuchen Zhou
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Patent number: 9792073Abstract: A method of managing logical unit numbers (LUNs) in a storage system includes identifying one or more LUN logical block address (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.Type: GrantFiled: February 9, 2015Date of Patent: October 17, 2017Assignee: Avalanche Technology, Inc.Inventors: Mehdi Asnaashari, Siamack Nemazie, Ruchirkumar D. Shah
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Patent number: 9793318Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.Type: GrantFiled: May 19, 2016Date of Patent: October 17, 2017Assignee: Avalanche Technology, Inc.Inventors: Kimihiro Satoh, Yiming Huai
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Patent number: 9786344Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.Type: GrantFiled: June 5, 2017Date of Patent: October 10, 2017Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Patent number: 9780300Abstract: The present invention is directed to an MTJ memory element comprising a magnetic free layer structure including one or more magnetic free layers that have a variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure including a first magnetic reference layer and a second magnetic reference layer with a perpendicular enhancement layer interposed therebetween, the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer.Type: GrantFiled: November 30, 2016Date of Patent: October 3, 2017Assignee: Avalanche Technology, Inc.Inventors: Yuchen Zhou, Bing K. Yen, Huadong Gan, Yiming Huai
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Patent number: 9748471Abstract: The present invention is directed to an STT-MRAM device comprising a plurality of memory elements. Each of the memory elements includes an MTJ structure that comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; a first perpendicular enhancement layer (PEL) formed adjacent to the magnetic free layer structure; a magnetic dead layer formed adjacent to the first PEL; and a magnetic fixed layer exchange coupled to the magnetic reference layer structure through an anti-ferromagnetic coupling layer. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a second PEL. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof.Type: GrantFiled: February 23, 2017Date of Patent: August 29, 2017Assignee: Avalanche Technology, Inc.Inventors: Yuchen Zhou, Zihui Wang, Huadong Gan, Yiming Huai
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Patent number: 9728240Abstract: A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state.Type: GrantFiled: March 14, 2014Date of Patent: August 8, 2017Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Patent number: 9727245Abstract: In accordance with a method of the invention, host data, accompanied by host LBA, is received from a host. If the host data is determined not to be a duplicate host data, an available intermediate LBA (iLBA) is identified and the host LBA is linked to the identified iLBA. During writing of the received host data to the SSDs, an available SLBA is identified and saved to a table at a location indexed by the identified iLBA. Accordingly, the next time the same host data is received, it is recognized as a duplicate host data and the host address accompanying it is linked to the same iLBA, which is already associated with the same SLBA. Upon this recognition, an actual write to the SSDs is avoided.Type: GrantFiled: May 26, 2015Date of Patent: August 8, 2017Assignee: Avalanche Technology, Inc.Inventors: Siamack Nemazie, Mehdi Asnaashari, Ruchirkumar D. Shah
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Patent number: 9691464Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.Type: GrantFiled: January 26, 2017Date of Patent: June 27, 2017Assignee: Avalanche Technology, Inc.Inventors: Ebrahim Abedifard, Parviz Keshtbod
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Perpendicular magnetic tunnel junction (pMTJ) with in-plane magneto-static switching-enhancing layer
Patent number: 9679625Abstract: An STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer, causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.Type: GrantFiled: November 2, 2015Date of Patent: June 13, 2017Assignee: Avalanche Technology, Inc.Inventors: Jing Zhang, Yiming Huai, Rajiv Yadav Ranjan, Yuchen Zhou, Zihui Wang, Xiaojie Hao -
Patent number: 9658780Abstract: A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.Type: GrantFiled: July 18, 2016Date of Patent: May 23, 2017Assignee: Avalanche Technology, Inc.Inventor: Siamack Nemazie
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Patent number: 9658859Abstract: A method of booting a system on chip (SoC) includes using an on-chip MRAM located in the SoC, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory (MRAM) located in and residing on the same semiconductor as the SoC. The method further includes directly executing the boot software from the on-chip MRAM by the SoC and directly accessing the user-personalized information from the MRAM by the SoC.Type: GrantFiled: November 26, 2013Date of Patent: May 23, 2017Assignee: Avalanche Technology, Inc.Inventors: Ngon Van Le, Ravishankar Tadepalli
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Patent number: 9652386Abstract: An embodiment of the present invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array and NAND array and a hybrid user area made of a combination of MRAM array and NAND array. The mass storage device further includes a controller with a host interface and a flash interface coupled to the MRAM and NAND flash memory devices through the flash interface.Type: GrantFiled: April 8, 2016Date of Patent: May 16, 2017Assignee: Avalanche Technology, Inc.Inventors: Mehdi Asnaashari, Siamack Nemazie
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Patent number: 9647202Abstract: The present invention is directed to an MRAM element comprising a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic reference layer structure, which includes a first and a second magnetic reference layers with a tantalum perpendicular enhancement layer interposed therebetween, an insulating tunnel junction layer formed adjacent to the first magnetic reference layer opposite the tantalum perpendicular enhancement layer, and a magnetic free layer formed adjacent to the insulating tunnel junction layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof.Type: GrantFiled: April 18, 2014Date of Patent: May 9, 2017Assignee: Avalanche Technology, Inc.Inventors: Huadong Gan, Yuchen Zhou, Yiming Huai, Zihui Wang, Xiaobin Wang
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Patent number: 9647032Abstract: The present invention is directed to a spin-orbitronics device including a magnetic comparison layer structure having a pseudo-invariable magnetization direction; a magnetic free layer structure whose variable magnetization direction can be switched by a switching current passing between the magnetic comparison layer structure and the magnetic free layer structure; an insulating tunnel junction layer interposed between the magnetic comparison layer structure and the magnetic free layer structure; and a non-magnetic transverse polarizing layer formed adjacent to the magnetic comparison layer structure. The pseudo-invariable magnetization direction of the magnetic comparison layer structure may be switched by passing a comparison current through the transverse polarizing layer along a direction that is substantially parallel to a layer plane of the transverse polarizing layer. The pseudo-invariable magnetization direction of the magnetic comparison layer structure is not switched by the switching current.Type: GrantFiled: August 20, 2015Date of Patent: May 9, 2017Assignee: Avalanche Technology, Inc.Inventors: Xiaobin Wang, Parviz Keshtbod, Kimihiro Satoh, Zihui Wang, Huadong Gan
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Patent number: 9646668Abstract: A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.Type: GrantFiled: October 27, 2014Date of Patent: May 9, 2017Assignee: Avalanche Technology, Inc.Inventors: Yuchen Zhou, Ebrahim Abedifard, Mahmood Mozaffari
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Patent number: 9634244Abstract: The present invention is directed to an MRAM element comprising a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic free layer structure has a variable magnetization direction substantially perpendicular to the layer plane thereof. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer plane thereof.Type: GrantFiled: March 24, 2016Date of Patent: April 25, 2017Assignee: Avalanche Technology, Inc.Inventors: Huadong Gan, Yiming Huai, Zihui Wang, Yuchen Zhou