Abstract: A stacked multijunction solar cell having a dielectric insulating layer system, a germanium substrate, which forms an underside of the multijunction solar cell, a germanium subcell and at least two III-V subcells, which follow each other in the specified order, the insulating layer system includes a layer sequence made up of at least one bottom insulating layer, which is integrally connected to a first surface section of the multijunction solar cell and a top insulating layer forming an upper side of the insulating layer system, and a metal coating of the multijunction solar cell is integrally and electrically conductively connected to a second surface section abutting the first surface section of the multijunction solar cell and is integrally connected to a section of the upper side of the insulating layer system, and the top insulating layer comprises amorphous silicon or is made up of amorphous silicon.

Abstract: A method for structuring an insulating layer on a semiconductor wafer, at least comprising the steps of: Provision of a semiconductor wafer with a top, a bottom and comprising multiple solar cell stacks, wherein each solar cell stack is a Ge substrate, which forms the bottom of the semiconductor wafer, a Ge subcell and at least two III-V subcells, in the above order, and at least one passage opening, which extends from the top to the bottom of the semiconductor wafer and has a connected side wall, an insulating layer two-dimensionally deposited on the top of the semiconductor wafer, on the side wall of the passage opening and/or on the bottom of the semiconductor wafer, and the deposition of an etch-resistant filling material by means of a printing process on an area of the top which comprises the passage opening, and into the passage opening.

Abstract: A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8·1015 cm?3, and a layer thickness of at least 10 ?m, wherein the cathode layer has a delta layer section with a layer thickness of 0.1 ?m to 2 ?m and a dopant concentration of at least 1·1019 cm?3.

Abstract: A stacked monolithic multijunction solar cell, which includes a first subcell having a p-n junction with an emitter layer and a base layer, the thickness of the emitter layer being less than the thickness of the base layer at least by a factor of ten, and the first subcell comprising a substrate having a semiconductor material from the groups III and V or a substrate from the group IV, and which further includes a second subcell arranged on the first subcell and a third subcell arranged on the second subcell, the two subcells each including an emitter layer and a base layer, and a tunnel diode and a back side field layer each being formed between the subcells, the thickness of the emitter layer being greater than the thickness of the base layer in each case between the second subcell and in the third subcell.

Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

Abstract: A Metalorganic chemical vapor phase epitaxy or vapor phase deposition apparatus, having a first gas source system, a reactor, an exhaust gas system, and a control unit, wherein the first gas source system has a carrier gas source, a bubbler with an organometallic starting compound, and a first supply section leading to the reactor either directly or through a first control valve, the carrier gas source is connected to an inlet of the bubbler through a first mass flow controller by a second supply section, an outlet of the bubbler is connected to the first supply section, and the carrier gas source is connected to the first supply section through a second mass flow controller by a third supply section, the first supply section is connected to an inlet of the reactor through a third mass flow controller.

Abstract: A solar cell stack includes a first semiconductor solar cell having a p-n junction made of a first material with a first lattice constant, a second semiconductor solar cell having a p-n junction made of a second material with a second lattice constant, and the first lattice constant being at least 0.008 ? smaller than the second lattice constant, and a metamorphic buffer. The metamorphic buffer is formed between the first semiconductor solar cell and the second semiconductor solar cell. The metamorphic buffer includes a series of at least five layers. The lattice constant increases in the series in the direction of the semiconductor solar cell. The lattice constants of the layers of the metamorphic buffer are larger than the first lattice constant. Two layers of the buffer having a doping and the difference in the dopant concentration between the two layers being greater than 4E17 cm?3.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A stacked multi-junction solar cell with a back-contacted front side, having a germanium substrate that forms a rear side of the multi-junction solar cell, a germanium sub-cell and at least two III-V sub-cells, successively in the named order, and at least one passage contact opening that extends from the front side of the multi-junction solar cell through the sub-cells to the rear side and a metallic connection contact that is guided through the passage contact opening. A diameter of the passage contact opening decreases in steps from the front side to the rear side of the multi-junction solar cell. The front side of the germanium sub-cell forms a first step having a first tread depth that circumferentially projects into the passage contact opening. The second step with a second tread depth circumferentially projects into the passage contact opening.

Abstract: A Metalorganic chemical vapor phase epitaxy or vapor phase deposition apparatus, having a first gas source system, a reactor, an exhaust gas system, and a control unit, wherein the first gas source system has a carrier gas source, a bubbler with an organometallic starting compound, and a first supply section leading to the reactor either directly or through a first control valve, the carrier gas source is connected to an inlet of the bubbler through a first mass flow controller by a second supply section, an outlet of the bubbler is connected to the first supply section, and the carrier gas source is connected to the first supply section through a second mass flow controller by a third supply section, the first supply section is connected to an inlet of the reactor through a third mass flow controller.

Abstract: A stacked III-V semiconductor photonic device having a second metallic terminal contact layer at least formed in regions, a highly doped first semiconductor contact region of a first conductivity type, a very low doped absorption region of the first or second conductivity type having a layer thickness of 20 ?m-2000 ?m, a first metallic terminal contact layer, wherein the first semiconductor contact region extends into the absorption region in a trough shape, the second metallic terminal contact layer is integrally bonded to the first semiconductor contact region and the first metallic terminal contact layer is arranged below the absorption region. In addition, the stacked III-V semiconductor photonic device has a doped III-V semiconductor passivation layer of the first or second conductivity type, wherein the III-V semiconductor passivation layer is arranged at a first distance of at least 10 ?m to the first semiconductor contact region.

Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping that changes from a first conductivity type to a second conductivity type on a surface of a substrate or a preceding layer in a reaction chamber from the vapor phase from an epitaxial gas flow comprising a carrier gas, at least one first precursor for an element from main group III, and at least one second precursor for an element from main group V, wherein when a first growth height is reached, a first initial doping level of the first conductivity type is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor, then the first initial doping level is reduced to a second initial doping level of the first or low second conductivity type.

Abstract: A III-V semiconductor pixel X-ray detector, including an absorption region of a first or a second conductivity type, at least nine semiconductor contact regions of the second conductivity type arranged in a matrix along the upper side of the absorption region, and optionally a semiconductor contact layer of the first conductivity type, a metallic front side connecting contact being arranged beneath the absorption region, and a metallic rear side connecting contact being arranged above each semiconductor contact region, and a semiconductor passivation layer of the first or the second conductivity type. The semiconductor passivation layer and the absorption region being lattice-matched to each other. The semiconductor passivation layer being arranged in regions on the upper side of the absorption region. The semiconductor passivation layer having a minimum distance of at least 2 ?m or at least 20 ?m with respect to each highly doped semiconductor contact region.

Abstract: A monolithic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of one another in the specified order, and the first subcell forms the top subcell and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer and the emitter doping in the second subcell is lower than the base doping.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 ?m2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Abstract: A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 ?m and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

Abstract: A stacked monolithic multi-junction solar cell having at least four subcells, wherein the band gap increases starting from the first subcell in the direction of the fourth subcell, each subcell has an n-doped emitter and a p-doped base, the emitter and the base of the first subcell each are formed of germanium, all following subcells each have at least one element of main group III and V of the periodic table, all subcells following the first subcell are formed lattice-matched to one another, a semiconductor mirror having a plurality of doped semiconductor layers with alternately different refractive indices is placed between the first and second subcell, the semiconductor layers of the semiconductor mirror are each formed n-doped and each have a dopant concentration of at most 5·1018 cm?3, the semiconductor mirror is placed between the first subcell and the first tunnel diode.

Abstract: A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, E F - E V < E G 2 applying to the layer (A) and E L - E F < E G 2 applying to the layer (B), with EF the energy position of the Fermi level, EV the energy position of the valence band, EL the energy position of a conduction band and EL?EV the energy difference of the semiconductor band gap EG, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.