Abstract: A telecommunications network node architecture is disclosed that enables a telecommunications network that uses automatic protection switching to be expanded to include more nodes than its standard protocol provides for without modifying the standard protocol or the existing nodes in the network. Although the illustrative embodiment is depicted as using the SONET/SDH protocol, it will be clear to those skilled in the art, after reading this specification, how to make and use embodiments of the present invention that use automatic protection switching with another protocol. The illustrative embodiment comprises: an automatic protection switching channel that defines an address space in the telecommunications network; a node that is uniquely identified by an address in the address space; and a node that is not uniquely identified by an address in the address space.

Abstract: A telecommunications node architecture is disclosed that facilitates the loop-back of a signal in an add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

Abstract: A SONET/SDH architecture is disclosed that enables the multiplexing of STS-1's from different SONET/SDH rings into a single STS-N for transmission via a single optical fiber, but while maintaining the association of each of the STS-1's with its respective SONET/SDH ring. For example, when an STS-48 carries 12 STS-1's from a first SONET/SDH ring and 12 STS-1's from a second SONET/SDH ring, the STS-48 carries: the automatic protection switching channel for the 12 STS-1's from the first SONET/SDH ring (with addresses specified in the address space of the first SONET/SDH ring); and the automatic protection switching channel for the 12 STS-1's from the second SONET/SDH ring (with addresses specified in the address space of the second SONET/SDH ring).

Abstract: An apparatus and method that extend the automatic protection switching protocol to address at least 256 network nodes. By using overhead bytes as extended APS node IDs, large single ring SONET/SDH systems can be avoided. This means APS messages that force every node into a single ring can be avoided and recovery performance from a break in the ring or a node fault can be improved. The protocol for the extended automatic protection switching channels takes multiple extended APS node IDs from tributary lines and merges those extended APS ID's into a single SONET/SDH stream on another line. Placement of the extended APS node ID's in the overhead bytes of SONET/SDH frames allows easy relay around each SONET/SDH ring.

Abstract: A composite add/drop multiplexor architecture is disclosed that facilitates the loop-back of a signal in a composite add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

Abstract: A multi-stage switching network that can hitlessly reconfigure itself comprising a controller that controls each stage separately. The controller designates the paths through each stage according to the set of paths currently active. If the set of paths changes, the controller sends a new set of paths to the first stage while using the old set of paths for the second stage during a first frame. On the next frame, the controller causes both stages to use the new set of paths.

Abstract: A serializer/deserializer pair with a discretionary loop-back mechanism is disclosed that enables a redundant high-bandwidth node architecture that benefits from the clever re-use of two identical integrated circuits. The first is an add/drop multiplexor and the second comprises the serializer/deserializer pair with discretionary loop-back. The illustrative embodiment comprises: a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words; a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and a multiplexor for selecting a third series of r-bit words from the first series of r-bit words and the second series of r-bit words; wherein r and s are both positive integers and r?s.

Abstract: An embodiment of this invention pertains to a system and method for balancing memory accesses to a low cost memory unit in order to sustain and guarantee a desired line rate regardless of the incoming traffic pattern. The memory unit may include, for example, a group of dynamic random access memory units. The memory unit is divided into memory channels and each of the memory channels is further divided into memory lines, each of the memory lines includes one or more buffers that correspond to the memory channels. The determination as to which of one or more buffers within a memory line an incoming information element is stored is based on factors such as the number of buffers pending to be read within each of the memory channels, the number of buffers pending to be written within each of the memory channels, and the number of buffers within each of the memory channels that has data written to it and is waiting to be read.

Abstract: An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i.e., the time to complete a process is known) and that it employs a pipelined “multiple instruction single date” (“MISD”) architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.

Abstract: A telecommunications node architecture is disclosed that comprises multiple add/drop multiplexors that are interconnected in a novel topology to enhance the reliability of the telecommunications network. Furthermore, the architecture of the illustrative embodiment ameliorates the well-known “add-before-drop” problem.

Abstract: An embodiment of this invention pertains to a digital circuit that shifts the phase of a clock signal. In this embodiment, multiple delay units, e.g., buffers, shift the clock signal multiple times and store a level of the clock signal within corresponding memory devices, e.g., flip-flops when triggered by the phase shifted clock signals. These levels may be at a high level (e.g., the clock signal has the value “1”) or a low level (e.g., the clock signal has the value “0”). A “phase selection table” stores multiple entries, each of the entries includes multiple clock level values. Each of the entries specifies values used to determine when the phase shifted clock signals transition from the high level to the low level. This transition point signifies a 180 degree phase shift. Using this transition point, other phase shifts can be determined.