Abstract: Disclosed is an over-current protection circuit, an over-current protection method and a display device. The over-current protection circuit provides an over-current protection for an operational amplifier and the over-current protection circuit comprises: a comparison module to compare a reference voltage and an output stage current sampling signal of the operational amplifier to determine whether an output stage current of the operational amplifier exceeds a protection threshold; a delay module to determine whether the output stage current of the operational amplifier exceeds the protection threshold for a time that reaches a preset time threshold, and output an over-current protection signal to turn off the operational amplifier when the output stage current of the operational amplifier exceeds the protection threshold for a time that reaches the preset time threshold.

Abstract: The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.

Abstract: A security defending method and an electronic apparatus are disclosed. The security defending method is applicable in a coprocessor, including: receiving a jump destination encryption request for the operation task; using mask configuration to perform first mask processing on the first jump destination address value to obtain a first intermediate jump destination address value; performing an authentication operation based on the first jump destination storage address, a key reference value corresponding to the operation task and the first intermediate jump destination address value, to obtain a first encryption result value; using the mask configuration to perform second mask processing on the first encryption result value to obtain a first intermediate encryption result value; performing an authentication operation on the first intermediate encryption result value and the first jump destination address value to obtain a first encryption jump destination address value.

Abstract: Disclosed is a calibration circuit, a calibration method for a filter and a filter device. The calibration circuit includes: a signal receiving terminal, receiving an output signal from the filter; a frequency detection module, obtaining a count value according to the output signal, the count value representing a frequency of the output signal; an adjustment module, adjusting the control signal according to the count value and a target value representing a target frequency, to adjust the frequency of the output signal provided by the filter until a calibration value, which allows the count value to be consistent with the target value, of the control signal is determined. The filter performs filtering according to the control signal with the calibration value in an operating stage. The calibration circuit performs feedback adjustment on the filter to achieve bandwidth calibration with high calibration accuracy and simple circuit structure.

Abstract: The present application provides a smart card interface, a data transmission method and a television chip. A first memory of the smart card interface is used for caching multiple pieces of indicator data corresponding to a video stream for a TV chip, and the multiple pieces of indicator data are used for determining a decryption key for the video stream. The transmitter is used for transmitting the multiple pieces of indicator data to a smart card sequentially; checking the multiple pieces of indicator data transmitted to the smart card to obtain a first check result of each of the multiple pieces of indicator data, where the first check result is used for indicating whether the smart card has successfully received the corresponding indicator data; and for any indicator data, determining whether to retransmit the indicator data to the smart card based on the first check result of the indicator data.

Abstract: Disclosed is a circuit and a method for video data conversion and a display device. The circuit comprises: a pixel splicing module, to sequentially receive each group of pixel data in each frame of image data in input video data, to perform pixel splicing on the received pixel data, and to output spliced pixel data; a data conversion module, to perform data processing on the spliced pixel data to convert each frame of image data into first image data representing a first part of the corresponding frame of image and second image data representing a second part of the corresponding frame of image. The first part at least comprises a left half part of the frame of image, the second part at least comprises a right half part of the frame of image. Data throughput requirements can be met while dynamic contrast and sharpening processing is performed.

Abstract: A method for wireless communication is provided, relating to field of wireless communication and including: determining, by an access point device, a first beacon frame and a first modulation mode; and transmitting, by the access point device, the first beacon frame to a station device according to the first modulation mode; where the first beacon frame is a target beacon frame, and the first modulation mode is an original modulation mode; or, the first beacon frame is an original beacon frame, and the first modulation mode is a target modulation mode; or, the first beacon frame is the target beacon frame, and the first modulation mode is the target modulation mode; a length of the target beacon frame is shorter than a length of the original beacon frame, and a transmission rate corresponding to the target modulation mode is greater than a transmission rate corresponding to the original modulation mode.

Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain. Prior to transmitting the equalization matching data to the source driver chip upon sending the link stable pattern to the source driver chip, the method further includes transmitting equalization gain configuration information to the source driver chip.

Abstract: Embodiments of the present application provide a GRPC-based chip test method, a GRPC-based chip test apparatus, and a storage medium. The GRPC-based chip test method comprises: determining a number of to-be-tested chips that actually need to be tested among to-be-tested chips, and issuing a corresponding number of remote instrument call requests according to the number of to-be-tested chips that actually need to be tested; acquiring each of the remote instrument call requests based on a GRPC protocol; and sorting all the remote instrument call requests to form a request execution sequence table, and controlling the test instrument to sequentially test the to-be-tested chips that actually need to be tested according to the request execution sequence table.

Abstract: A drive control method applicable to a timing controller and a drive circuit are provided. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

Abstract: Disclosed is a processing method for board-writing display and a related apparatus. The processing method includes: outputting a composited image frame of a current frame according to the current frame and a complete board-writing image most recently outputted by an extraction module transmitted by a first thread; transmitting, in a case that the extraction module is in an idle state, a previous frame and the current frame to the extraction module by a second thread, to output a complete board-writing image again; determining, in a case that the current frame is not a last frame, a next frame of the current frame as a next current frame by the first thread, and returning to perform above steps. Thus, technical problem of poor real-time video processing performance is solved, effectively avoiding video stuttering in an application which performs video processing while playing a video.

Abstract: The present application provides a method and an apparatus for information reception, a receiving device, a storage medium and a program product. The method includes: obtaining a receiving-length; receiving a beacon frame sent by a sending device based on the receiving-length to obtain target information, where the receiving-length is less than the total length of the beacon frame; performing packet analysis on the target information to obtain a first analysis result; and controlling, in case of determining that the first analysis result indicates that no downlink data from a sending device is to be sent to the receiving device, the receiving device to enter a sleep state. The method and apparatus for receiving information, device, storage medium and program product provided by the present application are used to reduce power consumption in receiving the beacon frame.

Abstract: The present application discloses a data transmission method, a primary apparatus, and a wireless network communication technology chip, and relates to the technical field of communications.

Abstract: A method and an apparatus for adjusting an instruction pipeline, a memory and a storage medium. The method for adjusting the instruction pipeline includes: receiving a move-type instruction, wherein the move-type instruction includes a target operand and a first source operand, and indicates to move a data of a source address indicated by the first source operand to a target address indicated by the target operand; receiving an object instruction located after the move-type instruction in an instruction sequence, wherein the object instruction includes an object source operand, indicating that an object operation is performed with a source address indicated by the object source operand; and replacing the object source operand in the object instruction with the first source operand of the move-type instruction to obtain a modified instruction, in response to the target operand of the move-type instruction being identify to the object source operand of the object instruction.

Abstract: A board-writing extraction method and a related device are provided. The board writing extraction method includes: obtaining a target object segmentation image of a writing-board image, wherein a contrast ratio between a target object and a non-target object in the target object segmentation image reaches a predetermined contrast ratio; converting, according to the target object segmentation image, a grayscale image of the writing-board image into a to-be-processed grayscale image with the board writing being highlighted; and performing binarization processing on the to-be-processed grayscale image to obtain a board-writing image of the writing-board image. The described method and related device can effectively reduce the noise in the board-writing image extracted from the writing-board image.

Abstract: The present application discloses a display driver integrated circuit and a control method thereof, relating to the technical field of display. An object of the present application mainly lies in that the display driver integrated circuit includes: a bus, a static random-access memory divided into a plurality of memory areas, and a plurality of transmission lines connected to the bus; wherein each of the memory areas includes at least two memory blocks; each of the transmission lines is respectively connected to a plurality of memory blocks in a corresponding manner, and the memory blocks connected to each of the transmission lines are not repeated.

Abstract: An apparatus and method for image compensation, a display driver, and a display are provided. The image compensation apparatus is applied to an electronic device with a curved screen and includes: a coordinate determination unit, configured to determine a row coordinate and a column coordinate for each of at least one pixel; a compensation coefficient determination unit, configured to: symmetrically map a row coordinate and a column coordinate of each of pixels located in an edge region of the curved screen, respectively, to obtain a target row coordinate and a target column coordinate of the pixel, and determine a compensation coefficient of the pixel based on the target row coordinate or the target column coordinate of the pixel; and a compensation unit, configured to determine a target pixel value of the pixel based on the compensation coefficient of the pixel and an original pixel value of the pixel.

Abstract: A display driver is provided. The display driver includes an OPR generating module, a brightness limiting module and a driving module. The OPR generating module is configured to generate a reference OPR corresponding to an image; the brightness limiting module is configured to acquire a plurality of brightness ranges and an initial brightness value corresponding to the image, one brightness range corresponding to one OPR range; the brightness limiting module is further configured to acquire a reduced brightness value corresponding to the reference OPR by performing interpolation at the reference OPR based on the initial brightness value, the plurality of brightness ranges and OPR ranges corresponding to the plurality of brightness ranges, the reduced brightness value being smaller than the initial brightness value; and the driving module is configured to drive the display panel to display the image based on the reference OPR and the reduced brightness value.

Abstract: An instruction flagging circuit includes: a first instruction detection sub-circuit for performing instruction detection on to-be-processed instructions to obtain a first detection result, wherein the first detection result includes a first conditional branch instruction and at least one non-jump instruction of the to-be-processed instructions, a jump range of the first conditional branch instruction is within a first range, and the non-jump instruction is to be executed when the first conditional branch instruction does not jump; and a first instruction flagging sub-circuit for setting, according to the first detection result, instruction flags for the first conditional branch instruction and the non-jump instruction to obtain target flagged instructions. The target flagged instructions indicate an instruction execution circuit to execute the non-jump instruction including the instruction flag when it is determined that the first conditional branch instruction jumps.

Abstract: The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.