Abstract: A switching regulator device for charging applications includes a transformer (18) which receives an AC input signal from an AC source (12) which is then rectified with a bridge rectifier (24). A regulation control circuit (26) is provided for regulating the output level of the bridge circuit (24) to a load (20). The regulation circuit (26) includes a switching element (62) which is operable to draw current from the AC source (12) in a periodic manner. The on/off duty cycle of the control to the switching element (62) will allow energy to be stored in a leakage inductance (36) of the transformer (18). The transformer (18) therefore comprises the switching inductance of a switching power supply with the leakage inductance (36) designed to provide adequate regulation for the voltage and current supplied to the load (10).

Abstract: A battery charge/discharge monitor circuit (10) is operable to be disposed in a battery pack (12) which can be connected to a battery (13). The monitor circuit (10) is operable to be connected to an external CPU (24) or similar system through a single wire communication port (22) for transferring information back and forth. There is also provided an external signal on a line (30) for indicating charge or discharge activity in the monitor circuit (10). The monitor circuit (10) is operable to collect information regarding the amount of charge input to the battery and the length of time that the charge is input to the battery and also the amount of charge that is removed from the battery and the length of time that the charge is removed. This information is stored in a memory block (62) for later access by the external CPU (24). This system also provides offset information to provide some type of compensation for non-linearities of the part.

Abstract: A reconfigurable integrated circuit chip includes an output terminal (42) which is connected to the output of an inverting amplifier (44). The integrated circuit chip (10) includes an output terminal (46) which is connected to one input of a comparator (22). The other end of comparator (22) is connected to an internal voltage reference device (48). The output of comparator (22) is connected to the input of the inverting amplifier (44). The integrated circuit chip (10) may be configured as a linear regulator when a transconductance device (14) is connected between a DC power supply (12) and a load and an integrator (24) is connected between terminal (42) and the control input of the transconductance device (14). The integrated circuit chip (10) is configured as a switching regulator when a gated switch (14) is connected between a DC power supply (12) and a switching node (65) wherein the gated switch (14) is gated by the signal output by the output terminal (42).

Abstract: A battery charge controller (50) is provided which includes a PWM switch controller (36) that is operable to control a switching regulator to supply current to a battery (10) in either a current regulation mode or a voltage regulation mode. A charge control (40) is operable to control the charging operation such that multiple modes of operation are selectable by an external programmable pin. The three modes provided are: a constant voltage mode, a dual-current mode and a pulse-current mode. The constant voltage mode provides for a conditioning state followed by a bulk charging state followed by a maintenance state. In the bulk charging state, current regulation is provided at a maximum current until a charged condition occurs, at which time the charger is placed in a voltage regulation mode.

Abstract: A four-way cache data memory is provided, having a cache data RAM (30) and a tag RAM (28). The tag RAM (28) is enabled to access one of the tags therein. This tag is compared with the tag portion of the received memory address to determine if a tag is stored therein. If a true comparison results, a HIT is indicated and this is utilized to enable a portion of the cache data RAM (30). The data in the enabled portion is then output on the data bus. Additionally, the data output of the cache data RAM (30) is inhibited unless it is determined that the cache data stored in the cache data RAM (30) is valid, this information stored in a status RAM (62).

Abstract: A battery charge controller (50) is provided which includes a PWM switch controller (36) that is operable to control a switching regulator to supply current to a battery (10) in either a current regulation mode or a voltage regulation mode. A charge control (40) is operable to control the charging operation such that multiple modes of operation are selectable by an external programmable pin. The three modes provided are: a constant voltage mode, a dual-current mode and a pulse-current mode. The constant voltage mode provides for a conditioning state followed by a bulk charging state followed by a maintenance state. In the bulk charging state, current regulation is provided at a maximum current until a charged condition occurs, at which time the charger is placed in a voltage regulation mode.

Abstract: A battery charger/protection device (10) is provided for charging a battery pack (12) comprised of four lithium ion cells. Each of the cells is selectively monitored by examining the voltage thereacross. An overvoltage condition is checked for a cell, an undervoltage condition for a cell is checked and an overcurrent condition for the entire battery pack (12) is checked. This is achieved by comparing the voltage with predetermined threshold voltages during the charging operation. This is a sequential operation wherein each of the batteries is sequentially examined in a continuous manner through the charging operation in accordance with a predetermined scheme. Switches (30) and (28) are provided for terminating a charging operation during charging. During operation, the undervoltage condition can be checked and the charger/protection device (10) placed in a sleep mode. The charger/protection device (10) provides a finite number of terminals for accessing any combination of cells.

Abstract: An integrated circuit with programmable output drive/program pins includes a plurality of output pads (30) which are each operable to interface with a separate and dedicated output driver (38). The output driver (38) is operable to drive an LED output device (14) in an operating mode. In a program mode, the driver (38) is disabled and a program buffer (40) enabled. At the same time, the LED output device (14) is disabled such that no impedance is presented to the output pad (30) due to operation of the LED output device (14). A programming resistor (18) is disposed between the pad (30) and one of three program reference voltages. A first program state is represented when the resistor (18) is tied to ground, a second program state is represented when the resistor (18) is tied to an open circuit and a third program state is represented when the resistor (18) is tied to a positive voltage.

Abstract: A realtime clock integrated circuit includes a memory (30) that has a plurality of addressable locations therein. The memory (30) has two portions, a lower portion and an upper portion. The lower portion is addressed by the seven least significant bits which are extracted from an input address bus (50). The seven address bits are latched in an address latch (54) for input to the address input of the memory (30). An eighth most significant address bit is received from an external line (64), which is attached to a separate bus on a personal computer other than that of the bus (50). The eighth most significant bit is latched in an address latch (62) for presentation to the most significant bit of the address input memory (30). When this most significant bit is high, the upper portion of the memory (30) is accessed.

Abstract: A battery detect circuit (32) is provided that is operable to dispose a sense resistor (50) in series with the battery to determine whether the charge is being provided to the battery or being extracted from the battery. The voltage across the sensor resistor (50) is sensed by a voltage/frequency converter (52). The voltage/frequency converter (52) is a differential structure comprised of two integrator structures (102) and (104) that are operable to utilize a switched capacitor configuration to drive comparators on the output thereof. Each of the integrator structures (102) and (104) has associated therewith passive elements and active elements. The integrators (102) and (104) have associated therewith integration capacitors (147) and (149). Additionally, there are two operational amplifiers (143) and (145) that provide the active components of each of the integrators (102) and (104).

Abstract: A reconfigurable integrated circuit chip includes an output terminal (42) which is connected to the output of an inverting amplifier (44). The integrated circuit chip (10) includes an output terminal (46) which is connected to one input of a comparator (22). The other end of comparator (22) is connected to an internal voltage reference device (48). The output of comparator (22) is connected to the input of the inverting amplifier (44). The integrated circuit chip (10) may be configured as a linear regulator when a transconductance device (14) is connected between a DC power supply (12) and a load and an integrator (24) is connected between terminal (42) and the control input of the transconductance device (14). The integrated circuit chip (10) is configured as a switching regulator when a gated switch (14) is connected between a DC power supply (12) and a switching node (65) wherein the gated switch (14) is gated by the signal output by the output terminal (42).

Abstract: An integrated circuit with programmable output drive/program pins includes a plurality of output pads (30) which are each operable to interface with a separate and dedicated output driver (38). The output driver (38) is operable to drive an LED output device (14) in an operating mode. In a program mode, the driver (38) is disabled and a program buffer (40) enabled. At the same time, the LED output device (14) is disabled such that no impedance is presented to the output pad (30) due to operation of the LED output device (14). A programming resistor (18) is disposed between the pad (30) and one of three program reference voltages. A first program state is represented when the resistor (18) is tied to ground, a second program state is represented when the resistor (18) is tied to an open circuit and a third program state is represented when the resistor (18) is tied to a positive voltage.

Abstract: A battery monitoring/control device includes a monitor/control device (35) that is operable to be integrated with a microprocessor system. The system includes a CPU (12) that interfaces with a data bus (14) and an address bus (16). The CPU (12) interfaces through a data line (40) with the control/monitor device (35) and control lines (28) and (34). Commands and data can be input to the control/monitor circuit (35) and data received therefrom. The control/monitor device (35) includes a controller/data register block (36) and a battery charge control/monitor block (44). The device (35) is operable to monitor the battery voltage of a secondary battery (46) during charging thereof and to control the rate of charge through a transistor (66). The battery monitor (90) determines when the voltage on the battery (46) reaches a predetermined level indicating full-charge.

Abstract: The low power voltage comparator with hysteresis includes a comparator (10) that is operable to receive the output from a battery (14) on the positive input thereof and the output of a battery (16) on the negative input thereof. An offset circuit (22) is provided in series with the voltage of the battery (14) and the comparator (10), and an offset circuit (24) is provided between the battery (16) and the comparator (10). The offset circuits (22) and (24) are adjustable by a hysteresis control circuit (26) to offset the voltage thereof for the non-selected battery to be higher than that for the selected battery such that the voltage drop across the offset for the non-selected battery is greater than that for the selected battery. When the voltage on the selected battery falls below the offset voltage of the non-selected battery, the hysteresis control then decreases the offset upon selecting the other battery and increases the offset or the battery that is deselected.

Abstract: A DC-DC converter is provided which is operable to drive a reactive circuit (10) that includes both a series inductor (12) and a capacitor (14) disposed between the output node and ground. The DC-DC converter includes two switches, a transistor switch (20) connected between a positive supply and an input node (16) and a second transistor (28) connected between the node (16) and ground. In one mode of operation, the transistors (20) and (28) operate in an asynchronous regulation mode with clock signals provided to the gates thereof. In a second asynchronous mode of operation, transistor (28) is turned off and replaced by its junction isolation diode (48). The transistor (20) is driven by a clock signal in accordance with an asynchronous regulation mode of operation. In a third mode of operation, the modified asynchronous duty cycle to the gate of transistor (20) is altered.

Abstract: A three-state input circuit operable to sense three separate logic states on an input pad (10) is operable to sense whether the current is sourced to the pad from a positive source or sinked from the pad to a negative source to provide two logic states. A third logic state is provided when it is determined that current is not being sourced to or sinked from the pad (10). A current source (36) is connected from a positive rail (14) through the source/drain path of an N-channel transistor (40) to the pad (10). This provides a sink current comparator function. A source current comparator function is provided by a current source (42) that is connected to the pad (10) through the source/drain path of a P-channel transistor (46) and to a negative voltage rail (18). The transistor (40) has a first bias voltage V.sub.B1 connected to the gate thereof and the transistor (46) has a second bias voltage V.sub.B2 connected to the gate thereof.

Abstract: A battery detect circuit (32) is connected to the battery with the current input to the battery and extracted from the battery measured with a sense resistor (50) and then converted to charge and discharge pulses with a V/F converter (52). A microcontroller (64) is operable to increment a Nominal Available Charge (NAC) register (180) during a charge operation, and to increment a Discharge Count Register (DCR) (184) during a discharge operation. The NAC register (180) indicates the available charge, which value is output to a display (34). The maximum value to which the NAC value can rise is limited by a value stored in the last measured discharge register (182). This value represents the value stored in the DCR (184) whenever the battery is discharged from an apparent full state to a fully discharged state. This results in a qualified transfer to the LMD register (182) such that no knowledge of the actual battery charge is necessary.

Abstract: A power resource management system includes a battery charging system (20) that is connected between a positive voltage terminal and a voltage sense terminal (15). An operating system (10), that in one mode operates off of the battery and in a second and charging mode operates off the power source (24), is connected between the positive terminal (12) and the voltage sense node (15). A sense resistor (16) is connected between the voltage sense node (15) and a ground terminal (18). The power source (24) is operable to deliver voltage across the positive terminal (12) and the negative terminal (18). The battery charger (20) includes a charge modulator (24) and a buck regulator which has a switch (26) that is controlled by the controller (34).

Abstract: A power control circuit (10) is operable to select between a backup battery (14) on a terminal (16) and a primary power supply voltage on a terminal (12) to output a voltage to a powered device (20). The two voltages are compared by a comparator (28) that drives a well bias node (44) with transistors (36) and (38). The comparator (28) selects the highest of two voltages on either the battery supply terminal (16) or the power supply terminal (12) to power the node (44), which node (44) is then connected to the wells of switching transistors (40) and (42) which are operable to select the battery terminals (16) in the event of a fail of the power supply on terminal (12). This decision is made with a power failure device (20). In the event that both the primary power supply voltage falls below a predetermined threshold and the battery supply voltage is at a higher level, the battery (14 ) is selected for output on the line (18).

Abstract: A battery detect circuit (32) is connected to the battery with the current input to the battery and extracted from the battery measured with a sense resistor (50) and then converted to charge and discharge pulses with a V/F converter (52). A microcontroller (64) is operable to increment a Nominal Available Charge (NAC) register (180) during a charge operation, and to increment a Discharge Count Register (DCR) (184) during a discharge operation. The NAC register (180) indicates the available charge, which value is output to a display (34). The maximum value to which the NAC value can rise is limited by a value stored in the last measured discharge register (182). This value represents the value stored in the DCR (184) whenever the battery is discharged from an apparent full state to a fully discharged state. This results in a qualified transfer to the LMD register (182) such that no knowledge of the actual battery charge is necessary.