Abstract: Methods and apparatuses for providing indications of missing landmarks in ultrasound images are described. Some embodiments are directed to apparatuses comprising a processing device configured to obtain data representing an ultrasound image, and determine whether the ultrasound image is clinically usable, wherein the determining comprises determining whether the ultrasound image lacks one or more landmarks. Determining whether the ultrasound image is clinically usable may further comprise determining a quality value representative of a quality of the ultrasound image and comparing the quality value to a threshold quality value. In some embodiments, landmarks comprise one or more anatomical features, such as a rib, a pleural line and an A line, a liver, and a kidney.

Abstract: Aspects of the technology described herein relate to instructing an operator to move an ultrasound device along a predetermined path relative to an anatomical area in order to collect first ultrasound data and second ultrasound data, the first ultrasound data capable of being transformed into an ultrasound image of a target anatomical view, and the second ultrasound data not capable of being transformed into the ultrasound image of the target anatomical view.

Abstract: The disclosed embodiments relate to a portable ultrasound device. Specifically, the disclosed embodiments relate to an acoustic lens positioned at an ultrasound probe. The acoustic lens may be configured for impedance matching and signal attenuation. In one embodiment, ultrasound signal attenuation is provided by forming an acoustic lens as a solid admixture of signal attenuating particles in a polymer matrix.

Abstract: Ultrasound devices are described. The ultrasound devices may be flexibly configured to output a certain number of multilines per channel of ultrasound data and to process certain channels of ultrasound data per processing cycle. The ultrasound device may then be configured to either output more multilines per channel and process fewer channels per processing cycle, or output fewer multilines per channel and process more channels per processing cycle. In other words, the circuitry may be configured to change to a configuration with increased resolution and increased processing time or to a configuration with decreased resolution and decreased processing time.

Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

Abstract: A universal ultrasound device having an ultrasound probe includes a semiconductor die; a plurality of ultrasonic transducers integrated on the semiconductor die, the plurality of ultrasonic transducers configured to operate a first mode associated with a first frequency range and a second mode associated with a second frequency range, wherein the first frequency range is at least partially non-overlapping with the second frequency range; and control circuitry configured to: control the plurality of ultrasonic transducers to generate and/or detect ultrasound signals having frequencies in the first frequency range, in response to receiving an indication to operate the ultrasound probe in the first mode; and control the plurality of ultrasonic transducers to generate and/or detect ultrasound signals having frequencies in the second frequency range, in response to receiving an indication to operate the ultrasound probe in the second mode.

Abstract: To implement a single-chip ultrasonic imaging solution, on-chip signal processing may be employed in the receive signal path to reduce data bandwidth and a high-speed serial data module may be used to move data for all received channels off-chip as digital data stream. The digitization of received signals on-chip allows advanced digital signal processing to be performed on-chip, and thus permits the full integration of an entire ultrasonic imaging system on a single semiconductor substrate. Various novel waveform generation techniques, transducer configuration and biasing methodologies, etc., are likewise disclosed. HIFU methods may additionally or alternatively be employed as a component of the “ultrasound-on-a-chip” solution disclosed herein.

Abstract: Aspects of the technology described herein relate to ultrasound device circuitry as may form part of a single substrate ultrasound device having integrated ultrasonic transducers. The ultrasound device circuitry may facilitate the generation of ultrasound waveforms in a manner that is power- and data-efficient.

Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

Abstract: Aspects of the technology described herein relate to an ultrasound device that may has a phase-locked loop (PLL) that includes a digitally-controlled oscillator (DCO). The DCO includes a plurality of current source unit cells with respective drain switches a plurality of current source unit cells with respective source switches. The plurality of current source unit cells with respective drain switches and the plurality of current source unit cells may have different circuit topologies. Switching on one of the plurality of current source unit cells with respective drain switches may cause a voltage transition at an internal node proceeding in one voltage direction and switching on one of the plurality of current source unit cells with respective source switches may cause a voltage transition at an internal node proceeding in the opposite voltage direction.

Abstract: Aspects of the disclosure described herein related to packaging an ultrasound-on-a-chip. In some embodiments, an apparatus includes an ultrasound-on-a-chip that has through-silicon vias (TSVs) and an interposer coupled to the ultrasound-on-a-chip and including vias, where the ultrasound-on-a-chip is coupled to the interposer such that the TSVs in the ultrasound-on-a-chip are electrically connected to the vias in the interposer. In some embodiments, an apparatus includes an ultrasound-on-a-chip having bond pads, an interposer that has bond pads and that is coupled to the ultrasound-on-a-chip, and wirebonds extending from the bond pads on the ultrasound-on-a-chip to the bond pads on the interposer.

Abstract: A method of forming an ultrasonic transducer device includes forming a curved membrane over a transducer cavity. A center portion of the curved membrane is closer to a bottom surface of the transducer cavity than with respect to radially outwardly disposed portions of the curved membrane.

Abstract: Aspects of the technology described herein relate to ultrasound circuits that employ a differential ultrasonic transducer element, such as a differential micromachined ultrasonic transducer (MUT) element. The differential ultrasonic transducer element may be coupled to an integrated circuit that is configured to operate the differential ultrasonic transducer element in one or more modes of operation, such as a differential receive mode, a differential transmit mode, a single-ended receive mode, and a single-ended transmit mode.

Abstract: A foldable processing device coupled to an ultrasound device is disclosed. In some embodiments, the foldable processing device may include a first panel having a first display screen, a second panel having a second display screen, and one or more hinges. The first panel and the second panel may be rotatably coupled by the one or more hinges. The foldable processing device may be in operative communication with an ultrasound device and configured to present different particular displays on the first and second display screens. In some embodiments, the foldable processing device may include a first panel, a second panel, a display screen, and one or more hinges. The first panel and the second panel may be rotatably coupled by the one or more hinges such that the display screen folds upon itself. The foldable processing device may be in operative communication with an ultrasound device and configured to present different particular displays on first and second portions of the display screen.

Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.