Abstract: Systems that allow for DFE functionality to be eliminated from the receiver side of a communication system and for a DFE-like functionality to be implemented instead at the transmitter side of the communication system are provided. By removing the DFE functionality from the receiver side, error propagation can be eliminated at the receiver and receiver complexity can be reduced drastically. At the transmitter side, the DFE-like functionality provides the same DFE benefits, and with the transmitter environment being noise-free, no errors can occur due noise boosting, for example. The DFE-like functionality at the transmitter side can be implemented using non-linear (recursive or feed-forward) pre-coders or a combination of non-linear pre-coders and linear filters, which can be configured to invert a net communication channel between the transmitter and the receiver. Embodiments particularly suitable for fiber optic channels and server backplane channels are also provided.

Abstract: The specification and drawings present a method, apparatus and software related product (e.g., a computer readable memory) for improving device discovery and D2D operation, e.g., in LTE wireless systems, by using control signaling provided by a wireless network (e.g., by an eNB). The discovery channel/channels which conveys discovery signal/signals are configured by a network (e.g., by the eNB) and are mapped to control channel/channels (e.g., one-to-one). After sending/receiving the discovery signal/signals, the D2D devices are monitoring control channel/channels to get current information for establishing the D2D communication among these D2D devices, the current information may include a resource allocation for the D2D communication and a device list of candidates for establishing the D2D communication.

Abstract: A framing mechanism may be provided that enables passing of messages over an addressed bus. This creates a form of information hiding, which passes information by converting an addressed bus interface to a message-based bus interface. Address-based information in a transaction may be replaced with additional information that specifies framing details comprising, for example, a check pattern and length information. The check pattern provides a mechanism for determining whether frame information may be valid. An end device may utilize this length information to determine an actual length of an incoming frame. The combination of the check pattern and the length information may provide a pattern for resynchronizing a data stream when errors are detected. The framing mechanism may operate over existing addressed buses without requiring host side controller hardware modifications and additional host side software driver may be utilized to add the framing information.

Abstract: A network switch for switching packets from a source to a destination includes a source port for receiving an incoming packet from a source, a destination port which contains a path to a destination for the packet, and a filter unit for constructing and applying a filter to selected fields of the incoming packet. The filter unit further includes filtering logic for selecting desired fields of the incoming packet and copying selected field information therefrom. The filtering logic also constructs a field value based upon the selected fields, and applies a plurality stored field masks on the field value. The switch additionally includes a rules table which contains a plurality of rules therein. The filtering logic is configured to perform lookups of the rules table in order to determine actions which must be taken based upon the result of a comparison between the field value and the stored filter masks and the rules table lookup.

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, complimentary transistor, current cource, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor.

Abstract: A printed antenna includes a 1st dipole section and a 2nd dipole section. The 1st dipole section includes a 1st radiation section and a 1st frequency section. The 2nd dipole antenna section includes a 2nd radiation section and a 2nd frequency section. The 1st and 2nd dipole antenna sections are electrically coupled together such that the currents flowing through the 1st and 2nd frequency sections substantially cancel and the current flowing through the 1st and 2nd radiation sections are substantially cumulative for a ½ wavelength antenna. For a full wavelength antenna, 1st and 2nd dipole antenna sections are electrically coupled together such that the currents flowing through the 1st and 2nd frequency sections are substantially cumulative and the current flowing through the 1st and 2nd radiation sections substantially cancel.

Abstract: A configurable multi-port modem includes a plurality of hybrids, a plurality of receivers, a plurality of transmitters, and a switching module. Each of the plurality of hybrids is operably coupled to provide 2 to 4 wire coupling for a corresponding one of a plurality of twisted pairs that are coupled to the configurable multi-port modem. Each of the plurality of receivers is operably coupled to convert inbound DSL signals into inbound data. Each of the plurality of transmitters is operably coupled to convert outbound data into outbound DSL signals. The switching module is operable to couple at least one of the plurality of hybrids to at least one of the plurality of receivers and to at least one of the plurality of transmitters based on a configuration control signal.

Abstract: A Class AB voltage-to-current converter includes a primary transconductance stage, secondary transconductance stage, and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the primary transconductance stage 12 becomes active before the secondary transconductance stage 14 with respect to the magnitude of a differential input voltage 18, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current convert.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths. The ALUs of the data path are coupled using a carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating a signal in response to a carry bit received over the carry chain, the signal comprises a saturation signal and a saturation value. The saturation signal is generated using logic that tests for saturation in the data path. The ALUs of the data path are further coupled using a right-going carry chain for transmitting the saturation signal back down the data path. The saturation signal is transmitted from the MSB ALU through the ALUs of the data path to the LSB ALU using a first back propagation channel.