Abstract: An optical coupler configured to couple light along a propagation direction is disclosed. The optical coupler includes a lower area. The lower area includes a waveguide including a first end, a second end, and an inversely tapered portion. The optical coupler includes an intermediary area arranged over, in a vertical direction, the lower area. The intermediary area includes two or more intermediary elements. The optical coupler includes an upper area arranged over the intermediary area. The upper area includes one or more upper elements.

Abstract: A device may include a host substrate with two or more circuit regions, one or more first stacks electrically connected to the circuit regions, and one or more second stacks providing electrical connections between the circuit regions. At least some of the second stacks may include an insulator wafer bonded to a die, where the die is bonded to at least one of the circuit regions. At least one of the second stacks may include a power distribution pathway to provide the electrical power to at least one of the circuit regions, which may include includes electrically-conductive vias through the insulator wafer and the die or capacitors in the die. Further, the die of at least one of the one or more second stacks may include electrical pathways to provide electrical connections between at least two of the two or more circuit regions.

Abstract: A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.

Abstract: Data rate that can be supported by a photodetector can be limited by the aperture size of the photodetector. In some embodiments, the minimum aperture diameter can be about 30 um. This limitation is due, for example, to an inability of the optics to focus the beam to a smaller spot, and the mechanical tolerances of the assembly process. The techniques described in the present disclosure can reduce the optical spot size and improve on the mechanical tolerances that are achievable, thereby improving the photodetector and VCSEL manufacturing processes and systems. A photodetector or VCSEL system design with higher data rate and lower production cost can be achieved using the techniques described herein.

Abstract: A semiconductor device, memory system, and method are provided. One example of the semiconductor device is disclosed to include a host interface that enables bi-directional communications with a host computer, a processor subsystem that enables processing of read or write requests received at the host interface, and one or more storage media interfaces, each of the one or more storage media interfaces being convertible between a first configuration and a second configuration, where the first configuration of a storage media interface enables a direct connection with a computer memory device, and where the second configuration of the storage media interface enables a connection with a plurality of computer memory devices via an expander and/or re-timer.

Abstract: An optical power transfer device with an embedded active cooling chip is disclosed. The device includes a cooling chip made of a semiconductor material, and a first subassembly and a second subassembly mounted on the cooling chip. The cooling chip comprises at least one metallization layer on a portion of a first surface of the cooling chip, at least one inlet through a second surface of the cooling chip, wherein the second surface is opposite to the first surface, at least one outlet through the second surface and one or more micro-channels extending between and fluidly coupled to the at least one inlet and the at least one outlet. A cooling fluid flows through the one or more micro-channels. The first subassembly is mounted on the at least one metallization layer and comprises a laser. The second subassembly comprises a phototransducer configured to receive a laser beam from the laser.

Abstract: An optical power transfer device with an embedded active cooling chip is disclosed. The device includes a cooling chip made of a semiconductor material, and a first subassembly and a second subassembly mounted on the cooling chip. The cooling chip comprises at least one metallization layer on a portion of a first surface of the cooling chip, at least one inlet through a second surface of the cooling chip, wherein the second surface is opposite to the first surface, at least one outlet through the second surface and one or more micro-channels extending between and fluidly coupled to the at least one inlet and the at least one outlet. A cooling fluid flows through the one or more micro-channels. The first subassembly is mounted on the at least one metallization layer and comprises a laser. The second subassembly comprises a phototransducer configured to receive a laser beam from the laser.

Abstract: Systems and methods are provided for detecting and mitigating a sleep deprivation attack (SDA). A method for detection of the SDA includes one of tracking power consumption rate of a device, incoming request signals received by the device, or an activity duration of one or more physical interfaces of the device. A system for mitigation of the SDA includes the device to be protected from the SDA, a counter to count request signals received by the device from another device, a counter attack circuit to pose one or more security challenges by sending a request message to the other device once a counted number of request signals exceeds a pre-determined number, and a control circuit to terminate connection with the other device if an expected reply based on the request message is not received from the other device within a pre-determined time duration.

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.

Abstract: Systems and methods relate to providing a transmit signal. The transmit signal can be provided in a transmitter circuit including a main pre-equalizer, a main power amplifier in communication with the main pre-equalizer, a replica pre-equalizer, and a replica power amplifier in communication with the replica pre-equalizer. The replica preamplifier is in communication with the main pre-equalizer, and control signals are provided to the main pre-equalizer to reduce distortion. The control signals are provided in response to an output signal of the replica power amplifier.

Abstract: A wireless power transmitter includes circuitry configured to determine a reflected impedance from a receiver coil at a transmitter coil and control a dead-time of one or more switching stages of a power conversion device based on the reflected impedance. A tunable matching network at the transmitter is controlled based on the reflected impedance and the dead-time of the one or more switching stages.

Abstract: A receiver includes circuitry configured to determine one or more first local oscillator (LO) harmonics that correspond to one or more first spectrum segments of a down-converted received signal based on characteristics of the received signal. The one or more first LO harmonics of the received signal are amplified by applying one or more first transconductance coefficients to one or more first harmonic selective transinductance amplifiers (TIAs) corresponding to the one or more first spectrum segments. Digitized outputs of the plurality of harmonic selective TIAs are calibrated based on an amount of signal leakage between the plurality of spectrum segments of the down-converted received signal.

Abstract: An electronic device includes circuitry configured to establish a steady-state connection with another device via a communication link. A backchannel data frame is detected in a steady-state data stream received from the other device via the communication link at a first predetermined data rate. The circuitry is configured to modify one or more signal transmission parameters based on signal information included in the backchannel data frame.

Abstract: A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.

Abstract: A device includes circuitry configured to transmit advertisement data to one or more electronic devices at a first advertisement rate. A presence or absence of the electronic devices is detected within communication range of the device based on a detection signal received from at least one of the one or more electronic devices. A predetermined advertisement rate is modified to correspond to a second advertisement rate based on the presence or absence of the one or more electronic devices.

Abstract: An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/ouput pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package.

Abstract: A device includes circuitry configured to determine characteristics of jammer signals associated with a first wireless protocol of another device. An amount of interference between the jammer signals and a first received signal at the device associated with a second wireless protocol is determined, and the jammer signals are filtered from the second received signal when the amount of interference between the jammer signals and the first received signal is greater than a first predetermined threshold.

Abstract: A network switch for network communications includes an embedded programmable state machine to monitor data flows through the switch. The programmable state machine is configured to retain selectable states of selectable data packet fields. Programmable switch logic operative with the programmable state machine is configured to output one or more potential actions to be taken based on a selectable computation of detected selectable states. The programmable state machine can be implemented with either table lookups or flexible logic.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.