Abstract: A device includes circuitry configured to determine characteristics of jammer signals associated with a first wireless protocol of another device. An amount of interference between the jammer signals and a first received signal at the device associated with a second wireless protocol is determined, and the jammer signals are filtered from the second received signal when the amount of interference between the jammer signals and the first received signal is greater than a first predetermined threshold.

Abstract: A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold and a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die. A pillar is disposed through the second mold layer and is coupled to a first metal layer disposed above the first dielectric layer. The first metal layer is coupled to the first die, and the pillar is coupled to a second metal layer disposed above the second dielectric layer.

Abstract: A network switch for network communications includes an embedded programmable state machine to monitor data flows through the switch. The programmable state machine is configured to retain selectable states of selectable data packet fields. Programmable switch logic operative with the programmable state machine is configured to output one or more potential actions to be taken based on a selectable computation of detected selectable states. The programmable state machine can be implemented with either table lookups or flexible logic.

Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

Abstract: A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: A transmit/receive switch architecture is provided which reuses a power amplifier's transformer as part of the low noise amplifier (LNA) input matching network. A front-end circuit includes a transmit/receive switch. The transmit/receive switch includes a transformer that includes primary winding and secondary winding. The transmit/receive also includes a transistor, where a drain of the transistor is connected to the secondary winding and a gate of the transistor is configured to receive a control signal. The transmit/receive switch operates as a receive switch when the control signal is low and inputs of the primary winding are either shorted or at open circuit. The transmit/receive switch operates as a transmit switch when the control signal is high.

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Abstract: A gaming object includes an orientation sensor that generates orientation data in response to the orientation of the gaming object. An actuator that generates interaction data in response to an action of a user. A transceiver sends an RF signal to a game device that indicates the orientation data and the interaction data. The game device generates display data for display on a display device that contains at least one interactive item, and wherein the at least one interactive item is interactive in response to the orientation data and the interaction data.

Abstract: A game console includes a receiver that receives motion data in response to motion of a gaming object. A trajectory generation module generates trajectory data based on the motion data and based on a motion prediction model. A processor executes a gaming application based on the trajectory data to generate display data.

Abstract: A system and method includes a power control circuit for controlling first power from a power supply provided to a first circuit includes a first stage and a second stage. The first stage includes a low power energy detector and a first power switch. The low power energy detector is configured to provide second power via the first switch in response to energy. The second stage includes a signal detector configured to detect a characteristic of a signal associated with the energy in response to the second power. The signal detector is configured have the first power provided to the first circuit in response to the characteristic being detected.

Abstract: A regulator circuit includes a multiphase ramp generator circuit, an amplifier circuit configured to receive a plurality of phase sense signals and provide a plurality of respective error signals, and an adder circuit configured to receive the error signals and ramp generator signals. The ramp generator signals are received from the multiphase ramp generator circuit and the adder circuit is configured to provide a plurality of respective adjusted ramp generator signals. The regulator can be a multiphase switching regulator circuit.

Abstract: A device includes circuitry configured to implement one or more PHY communications protocols to simultaneously communicate with one or more stations via communication links on one or more wireless networks, communicate with additional devices via a backhaul network, and exchange collaboration data, including at least one of protocol data or collaborative beamforming data, with the additional devices via the backhaul network to maintain signal parameters of communications signals with the one or more stations.

Abstract: A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g.

Abstract: The present disclosure describes a semiconductor wafer testing environment for routing signals used for testing integrated circuits formed onto a semiconductor wafer. The semiconductor wafer testing environment includes a semiconductor wafer tester to control overall operation and/or configuration of the semiconductor wafer testing environment and a semiconductor wafer prober to test the integrated circuits formed onto the semiconductor wafer. The semiconductor wafer prober includes a probe card having a transmission line coupler formed onto a flexible substrate. The transmission line coupler includes multiple transmission line coupling blocks that extend radially from a central point of the flexible substrate in a circular manner.

Abstract: A media processing device, such as a set top box, having a plurality of selectable hardware and software components for supporting multiple media pathways providing differing levels of security. In general, each security level corresponds to a particular certification service boundary definition(s) or key/authentication and security management scheme for managing resources such as hardware acceleration blocks and software interfaces. Different sets of components may be adaptively employed to ensure composited compliance with one or more security constraints and to address component unavailability. Security constraints may be applied, for example, on a source or media specific basis, and different versions of a media item may be provided over multiple pathways providing corresponding levels of security. In one embodiment, a service operator or content provider may provide requisite certification or security requirements, or otherwise assist in selection of pathway components.

Abstract: A power line communication device comprises a plurality of transformers in series. These transformers are used to increase the voltage of a digitally encoded signal in a stepwise fashion prior to being coupled into a power line. While a transmit path includes at least a first transformer and a second transformer in series, a receive path may include only one of these two transformers. For example a receive path may include only the first transformer, or include the first transformer and a third transformer. The net ratio of voltage increase and decrease may be different in the transmit and receive paths.

Abstract: The present disclosure is directed to apparatuses for preventing significant amounts of common mode noise from a PHY transceiver, such as an Ethernet PHY transceiver, from coupling to an unshielded twisted-pair cable. The apparatuses can provide common mode noise isolation, while limiting any common mode noise to differential mode noise (CM-DM) conversion. Common mode noise is generally ignored by a PHY transceiver that receives a differential data signal because of differential signaling. However, when common mode noise is converted to differential mode noise, then data errors can result. Thus, limiting any CM-DM conversion is important.

Abstract: A wireless communication device (alternatively, device, WDEV, etc.) includes at least one processing circuitry configured to support communications with other WDEV(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processing circuitry, among other possible circuitries, components, elements, etc. to support communications with other WDEV(s) and to generate and process signals for such communications. A WDEV determines capabilities of other WDEVs and generates a first orthogonal frequency division multiple access (OFDMA) frame that includes resource unit (RU) allocation specified for the other WDEVs and media access controller (MAC) padding (e.g., selected based on capability of at least one of the other WDEVs. The WDEV then transmits the first OFDMA frame to the other WDEVs to be processed by them and then receives a second OFDMA frame from the other WDEVs based on the RU allocation.

Abstract: Disclosed is an apparatus, method and computer program which frequency shifts a received signal by a first frequency value and low-pass filters the frequency shifted received signal at a first cutoff frequency to filter out a plurality of adjacent carrier frequencies. Parallel baseband processing is then performed on two or more adjacent carrier frequencies among the plurality of adjacent carrier frequencies based upon an adjacent carrier power criterion. In certain examples, the parallel baseband processing is adapted for detecting a frequency correction burst in two or more adjacent Global System for Mobile Communications carrier frequencies or an Enhanced Data Rates for Global System for Mobile Communications Evolution carrier frequencies.