Abstract: Systems and methods are provided for detecting and mitigating a sleep deprivation attack (SDA). A method for detection of the SDA includes one of tracking power consumption rate of a device, incoming request signals received by the device, or an activity duration of one or more physical interfaces of the device. A system for mitigation of the SDA includes the device to be protected from the SDA, a counter to count request signals received by the device from another device, a counter attack circuit to pose one or more security challenges by sending a request message to the other device once a counted number of request signals exceeds a pre-determined number, and a control circuit to terminate connection with the other device if an expected reply based on the request message is not received from the other device within a pre-determined time duration.

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.

Abstract: Systems and methods relate to providing a transmit signal. The transmit signal can be provided in a transmitter circuit including a main pre-equalizer, a main power amplifier in communication with the main pre-equalizer, a replica pre-equalizer, and a replica power amplifier in communication with the replica pre-equalizer. The replica preamplifier is in communication with the main pre-equalizer, and control signals are provided to the main pre-equalizer to reduce distortion. The control signals are provided in response to an output signal of the replica power amplifier.

Abstract: A wireless power transmitter includes circuitry configured to determine a reflected impedance from a receiver coil at a transmitter coil and control a dead-time of one or more switching stages of a power conversion device based on the reflected impedance. A tunable matching network at the transmitter is controlled based on the reflected impedance and the dead-time of the one or more switching stages.

Abstract: A receiver includes circuitry configured to determine one or more first local oscillator (LO) harmonics that correspond to one or more first spectrum segments of a down-converted received signal based on characteristics of the received signal. The one or more first LO harmonics of the received signal are amplified by applying one or more first transconductance coefficients to one or more first harmonic selective transinductance amplifiers (TIAs) corresponding to the one or more first spectrum segments. Digitized outputs of the plurality of harmonic selective TIAs are calibrated based on an amount of signal leakage between the plurality of spectrum segments of the down-converted received signal.

Abstract: An electronic device includes circuitry configured to establish a steady-state connection with another device via a communication link. A backchannel data frame is detected in a steady-state data stream received from the other device via the communication link at a first predetermined data rate. The circuitry is configured to modify one or more signal transmission parameters based on signal information included in the backchannel data frame.

Abstract: A device includes circuitry configured to transmit advertisement data to one or more electronic devices at a first advertisement rate. A presence or absence of the electronic devices is detected within communication range of the device based on a detection signal received from at least one of the one or more electronic devices. A predetermined advertisement rate is modified to correspond to a second advertisement rate based on the presence or absence of the one or more electronic devices.

Abstract: A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.

Abstract: An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/ouput pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package.

Abstract: A device includes circuitry configured to determine characteristics of jammer signals associated with a first wireless protocol of another device. An amount of interference between the jammer signals and a first received signal at the device associated with a second wireless protocol is determined, and the jammer signals are filtered from the second received signal when the amount of interference between the jammer signals and the first received signal is greater than a first predetermined threshold.

Abstract: A network switch for network communications includes an embedded programmable state machine to monitor data flows through the switch. The programmable state machine is configured to retain selectable states of selectable data packet fields. Programmable switch logic operative with the programmable state machine is configured to output one or more potential actions to be taken based on a selectable computation of detected selectable states. The programmable state machine can be implemented with either table lookups or flexible logic.

Abstract: A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold and a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die. A pillar is disposed through the second mold layer and is coupled to a first metal layer disposed above the first dielectric layer. The first metal layer is coupled to the first die, and the pillar is coupled to a second metal layer disposed above the second dielectric layer.

Abstract: A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

Abstract: A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: A transmit/receive switch architecture is provided which reuses a power amplifier's transformer as part of the low noise amplifier (LNA) input matching network. A front-end circuit includes a transmit/receive switch. The transmit/receive switch includes a transformer that includes primary winding and secondary winding. The transmit/receive also includes a transistor, where a drain of the transistor is connected to the secondary winding and a gate of the transistor is configured to receive a control signal. The transmit/receive switch operates as a receive switch when the control signal is low and inputs of the primary winding are either shorted or at open circuit. The transmit/receive switch operates as a transmit switch when the control signal is high.

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Abstract: A game console includes a receiver that receives motion data in response to motion of a gaming object. A trajectory generation module generates trajectory data based on the motion data and based on a motion prediction model. A processor executes a gaming application based on the trajectory data to generate display data.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.