Abstract: Systems and methods are provided for detecting and mitigating a sleep deprivation attack (SDA). A method for detection of the SDA includes one of tracking power consumption rate of a device, incoming request signals received by the device, or an activity duration of one or more physical interfaces of the device. A system for mitigation of the SDA includes the device to be protected from the SDA, a counter to count request signals received by the device from another device, a counter attack circuit to pose one or more security challenges by sending a request message to the other device once a counted number of request signals exceeds a pre-determined number, and a control circuit to terminate connection with the other device if an expected reply based on the request message is not received from the other device within a pre-determined time duration.

Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.

Abstract: An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/ouput pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package.

Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: A transmit/receive switch architecture is provided which reuses a power amplifier's transformer as part of the low noise amplifier (LNA) input matching network. A front-end circuit includes a transmit/receive switch. The transmit/receive switch includes a transformer that includes primary winding and secondary winding. The transmit/receive also includes a transistor, where a drain of the transistor is connected to the secondary winding and a gate of the transistor is configured to receive a control signal. The transmit/receive switch operates as a receive switch when the control signal is low and inputs of the primary winding are either shorted or at open circuit. The transmit/receive switch operates as a transmit switch when the control signal is high.

Abstract: A broadband digital transmitter is disclosed. The digital transmitter includes a vector decomposer circuit, a phase selector circuit, and a digital power amplifier (DPA). The vector decomposer circuit receives baseband in-phase (I) and quadrature (Q) signals and decomposes the baseband I and Q signals into an offset envelope signal and a non-offset envelope signal. The phase selector circuit receives a plurality of phase offset local oscillator (LO) signals and outputs, responsive to the baseband I and Q signals, offset LO signals and non-offset LO signals. The DPA processes the offset envelope signal, the non-offset envelope signal, the offset LO signals, and the non-offset LO signals to generate an output signal of the digital transmitter.

Abstract: A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g.

Abstract: The present disclosure describes a semiconductor wafer testing environment for routing signals used for testing integrated circuits formed onto a semiconductor wafer. The semiconductor wafer testing environment includes a semiconductor wafer tester to control overall operation and/or configuration of the semiconductor wafer testing environment and a semiconductor wafer prober to test the integrated circuits formed onto the semiconductor wafer. The semiconductor wafer prober includes a probe card having a transmission line coupler formed onto a flexible substrate. The transmission line coupler includes multiple transmission line coupling blocks that extend radially from a central point of the flexible substrate in a circular manner.

Abstract: The present disclosure is directed to apparatuses for preventing significant amounts of common mode noise from a PHY transceiver, such as an Ethernet PHY transceiver, from coupling to an unshielded twisted-pair cable. The apparatuses can provide common mode noise isolation, while limiting any common mode noise to differential mode noise (CM-DM) conversion. Common mode noise is generally ignored by a PHY transceiver that receives a differential data signal because of differential signaling. However, when common mode noise is converted to differential mode noise, then data errors can result. Thus, limiting any CM-DM conversion is important.

Abstract: A wireless communication device (alternatively, device, WDEV, etc.) includes at least one processing circuitry configured to support communications with other WDEV(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processing circuitry, among other possible circuitries, components, elements, etc. to support communications with other WDEV(s) and to generate and process signals for such communications. A WDEV determines capabilities of other WDEVs and generates a first orthogonal frequency division multiple access (OFDMA) frame that includes resource unit (RU) allocation specified for the other WDEVs and media access controller (MAC) padding (e.g., selected based on capability of at least one of the other WDEVs. The WDEV then transmits the first OFDMA frame to the other WDEVs to be processed by them and then receives a second OFDMA frame from the other WDEVs based on the RU allocation.

Abstract: The present disclosure is directed to systems, apparatuses, and methods for monitoring the frequency spectrum of signals transmitted by a PLC device over a PLC network to detect and correct potential EMC regulation violations due to intermodulation (IMD) products created by the interaction of the transmitted signals with one or more non-linear devices on the PLC network. Once an IMD issue is detected, the systems, apparatuses, and methods can reduce the injected power of signals transmitted by the PLC device at the frequencies (or range of frequencies) that result in a EMC regulation violation. In addition, the systems, apparatuses, and methods can reduce the injected power of signals transmitted by the PLC device at all times or during times that the non-linear devices are interacting and generating IMD products.

Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Abstract: Wireless access points within a GPS-Unavailable environment can provide location services to user equipment devices within the environment provided that the access points are aware of their precise locations. In order to calibrate the locations of the wireless access points, a user equipment is moved to specific locations within the environment. At each of those locations, the user equipment transmits calibration signals that include the transmission location as well as a timestamp of the transmission time. Upon receipt by the access points, these signals are timestamped with a reception timestamp by a clock that is synchronized with the clock of the user equipment. After accumulating sufficient calibration information from a sufficient number of calibration locations, the access points can accurately determine their locations using trigonometric and other functions.

Abstract: According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

Abstract: A multi-cast multi-poll scheme for Bluetooth law energy (BLE) technology to be used by one or more mobile devices within a communication environment is disclosed. A broadcaster communication device comprises a transceiver that is configured to communicate with a plurality of recipient communication devices. The broadcaster communication device further comprises a controller that is configured to transmit a packet to the plurality of recipient communication devices and to receive, at predefined time intervals, responses from the plurality of recipient communication devices according to a pre-negotiated order without transmitting any additional packets.

Abstract: Methods and systems for enabling coexistence of multiple potentially interfering wireless components in a device are provided. A device may include a wireless module using a proprietary protocol and one or more modules using standardized protocols. The device further includes a coexistence arbitration module configured to arbitrate access to a shared communication medium among the wireless modules based on assertion of medium access requests by the modules and the associated priority of the asserted medium access requests. When multiple medium access requests have the same priority, precedence for access to the shared medium is determined based on additional criteria. The coexistence arbitration module may be a separate module or may be integrated into another module or distributed among the modules. The device may include a host processor for altering transmission characteristics of a module to increase the likelihood that another module can receive data within a reasonable time period.

Abstract: Currently, there exists low power Ethernet PHY solutions running at 10 Gbps over twin-ax cables with SFP+ connectors. However, the cost and range of these cables, along with the size of the connectors, do not match the requirements of in-vehicle networks. If the cable is replaced with a single pair of shielded or coaxial cables, a different mechanism is needed to provide bi-directional communication. Time division duplexing (TDD) can be used to emulate full duplex communication over the single pair of cables by taking turns, in time, transmitting data over the pair of cables in each direction.

Abstract: In some aspects, the disclosure is directed to methods and systems for encoding and sharing media clips via a social networking provider responsive to a user interaction via a single “like” or “share” button. Media may be constantly buffered as the user watches the program, such that the user need not initiate recording, enabling the user to quickly share amusing or media clips as they happen live. The device may decode, scale or subsample, and compress or re-encode the media to take up less space in a buffer of the device and/or to comply with copyright fair use requirements. Responsive to the user interaction or “share” command, the device may transfer the contents of the buffer to a social media service along with instructions to generate a post to the social network identifying the user, media, and/or buffer contents.

Abstract: The present disclosure provides an apparatus and method for measuring echo responses of communication links used in in-vehicle networks with high resolution and high dynamic range, allowing for diagnostics of various failures and/or degradations with high precision. Additional information can be provided to indicate signaling quality, insertion loss, and return loss of the communication links used in in-vehicle networks. Together, these measures and information can provide a comprehensive diagnostic capability that improves network reliability and safety of in-vehicle networks.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.