Abstract: LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating are successively and alternatively performed on bit edge messages for a predetermined number of decoding iterations or until a sufficient degree of precision is achieved. The symbol node updating of the bit edge messages involves using symbol metrics corresponding to the symbol being decoded as well as the bit edge messages most recently updated by check node updating. The check node updating of the bit edge messages involves using the bit edge messages most recently updated by symbol node updating. The symbol node updating also involves computing possible soft symbol estimates for the symbol during each decoding iteration.

Abstract: Hard disk drive progressive channel interface. A novel approach is presented by which the interface between a channel circuitry and a controller circuitry, such as those which can be implemented within a hard disk drive (HDD). Because of the location in which the disk management operations are supported and performed within the channel circuitry, the interface between the channel circuitry and the controller circuitry can be implemented to support direct memory access (DMA) protocol data transfers and control there between. Because the disk management operations are supported within the channel circuitry, as opposed to the controller circuitry, then the disk management operations need not necessarily comply with an interface between the channel circuitry and the controller circuitry. This allows for better control of the disk management operations as well as a much broader range and type of interface that can be employed for the interface between the two circuitries.

Abstract: Hard disk controller having multiple, distributed processors. A novel approach is presented by which a separate and dedicated processor is provisioned to service each of a plurality of control loops within a hard disk drive (HDD) controller. For example, a first processor is implemented to service a servo control loop, a second processor is implemented to service channel interfacing, and a third processor is implemented to service host interfacing. In some embodiments, the channel and host interfacing are performed using protocol processors implemented within each of a disk manager module and a host manager module, respectively.

Abstract: Timing recovery optimization using disk clock. A novel means is presented to perform and provide control of the sampling frequency of a signal that is read from a disk within a hard disk drive (HDD). Two separate, yet somewhat cooperating control loops are employed to provide feedback control of the sampling frequency of the signal that is read from disk. A timing recovery loop and a disk clock loop operate in conjunction with one another according to some desired manner (which can be predetermined or adaptive) to ensure that the sampling of the signal is performed to a very accurate degree. In one implementation, the timing recovery loop governs the sampling rate until the disk clock loop has locked, from which time either the disk clock loop govern the sampling or some combination of the signals provided from the two loops govern the sampling.

Abstract: An integrated circuit (IC) assembly includes circuitry, radio frequency identification (RFID) tag circuitry, and an antenna structure. The circuitry is operable to perform at least one function. The RFID tag circuitry is coupled to process an RFID signal to produce a supply voltage for the RFID tag circuitry and to produce a response RFID signal. The response RFID signal includes information regarding at least one of: a device including the IC assembly, the IC assembly, and the at least one function. The antenna structure is coupled to receive the RFID signal and to provide the RFID signal to the RFID tag circuitry and to transmit the response RFID signal.

Abstract: Optimal synchronization mark/address mark construction. These marks can generally be referred to as sync marks. A novel means is presented by which sync marks can be generated for use within a variety of communication systems including HDD systems. The sync marks generated hereby have a largest possible minimum distance measurement that ensures highly accurate detection of the transition between the data portion and the preamble portion of information that is processed. Various types of distance measurement criteria can be employed, including a Euclidean distance measurement or a Hamming distance measurement, when selecting the sync mark from among a plurality of possible sync marks.

Abstract: A host interface module is operable to couple the disk drive to a host device. The host interface module includes a plurality of personality modules, each of the plurality of personality modules, when coupled to the host device, is operable to accept read and write commands and transfer data to and from the host device in a corresponding one of a plurality of host interface protocols. A universal host module decodes read and write commands from the host device and transports data written to and read from the disk drive via a first of the plurality of personality modules. A multiplexer selectively couples the first of the plurality of personality modules to the universal host module in response to a selection signal. A system interface couples the universal host module to a processor and a memory of the disk controller.

Abstract: Minimal hardware implementation of non-parity and parity trellis. A novel means is presented by which more than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. A very efficient means is provided with rules which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

Abstract: An impedance transformer includes a first winding and a second winding. The first winding includes a first plurality of winding components, wherein each of the first plurality of winding components is on a corresponding layer of a first set of layers of a supporting substrate. The second winding includes a second plurality of winding components, wherein each of the second plurality of winding components is on a corresponding layer of a second set of layers of the supporting substrate and the first and second sets of layers are interleaved. The first winding has a first impedance within a desired frequency range and the second winding has a second impedance within the desired frequency range, where the first and second impedances are based on at least one of spacing, trace width, and trace length of the first and second plurality of winding components.

Abstract: A device includes a plurality of IC assemblies, where each IC assembly includes circuitry and RFID tag circuitry. The circuitry is operable to perform at least one function. The RFID tag circuitry is operable to: receive an RFID signal; process the RFID signal to produce a supply voltage for the RFID tag circuitry; interpret the RFID signal to determine whether the RFID tag circuitry is to respond to the RFID signal; and when the RFID tag circuitry is to respond to the RFID signal, transmit a response RFID signal, wherein the response RF signal includes information regarding at least one of: the device, at least one of the plurality of IC assemblies, and one or more of the at least one function.

Abstract: An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

Abstract: A servo field preamble detector includes an upsampling module that generates a plurality of upsampled read samples by upsampling a read signal by an upsampling factor. An interpolation filter module generates a plurality of interpolated read samples from the plurality of upsampled read samples. A peak detection module identifies a plurality of peak samples from the plurality of interpolated read samples. A magnitude estimation module generates a magnitude estimation signal from the plurality of peak samples. A comparison module compares the magnitude estimation signal to a magnitude threshold and asserts a servo preamble detection signal when the magnitude estimation signal compares favorably to the magnitude threshold.

Abstract: A servo writer includes a servo data generation module that generates servo data corresponding to a plurality of servo wedges and a plurality of tracks of a disk, the servo data including burst data that is repetition coded. A servo write module writes the servo data on the disk.

Abstract: An antenna structure includes first and second antennas. The first antenna has a first geometry corresponding to a first frequency. The second antenna has a second geometry corresponding to a second frequency. The second antenna is proximal to the first antenna and utilizes electrical-magnetic properties of the first antenna to transceive signals at the second frequency.

Abstract: A controller includes a combining module that generates a total control signal for the drive device of a disk drive by combining a feedback control signal and a feedforward control signal. A feedback control module generates the feedback control signal in response to at least one state of the drive device. A feedforward control module generates the feedforward control signal based on a smoothing function and a feedforward control function. The smoothing function is determined by evaluating a plurality of candidate smoothing functions by determining a smoothness factor associated with the control signal that results from each of the plurality of candidate smoothing functions, and selecting the smoothing function as one of the plurality of candidate smoothing functions, based on the smoothness factor.

Abstract: A power amplifier for use in a transmitter includes a first transistor having an input, a first node and a second node, a second transistor having an input, a first node and a second node and a digital to analog conversion module. The input of the first transistor is operably coupled to receive a first input, while the input of the second transistor is operably coupled to receive a second input. The second nodes of the first and second transistors provide an output of the power amplifier. The digital to analog conversion module is operably coupled to control current through the first and second transistors based on at least one of a power control signal and an amplitude modulation control signal.

Abstract: A video processing device that generates sub-frame metadata for use in modifying a sequence of original video frames includes a video interface for receiving video data representing the sequence of original video frames, a user interface for receiving as user input sub-frame information identifying a sub-frame corresponding to a region of interest within a scene depicted in at least one frame of the sequence of original video frames and processing circuitry for generating the sub-frame metadata from the sub-frame information. Editing information associated with each sub-frame may also be included in the sub-frame metadata. Targeted sub-frame metadata can be specifically generated for use with a particular screen or screen size. A first player with a small screen and a second player with a larger screen may each receive different sub-frame metadata files, while both receive the same original video.

Abstract: An electrostatic-discharge/impedance-matching circuit for use in radio frequency (RF) integrated circuits. The electrostatic-discharge/impedance-matching circuit comprises at least one shunt circuit operable to shunt current related to an over-voltage condition and at least one series element operably coupled to the shunt element. The shunt element and series element in combination provide electrostatic discharge protection for the RF signal processing circuit elements on the integrated circuit and also provide a matched input impedance for an incoming RF signal. Various alternate embodiments of the electrostatic-discharge/impedance-matching circuit include first and second shunt elements and a series element operably connected in combination to provide optimal electrostatic discharge protection and impedance matching.

Abstract: A method for multiple input multiple output wireless communication begins by determining protocols of wireless communication devices within a proximal region. The method continues by determining whether the protocols of the wireless communication devices within the proximal region are of a like protocol. The method continues by determining the number of transmit antennas. The method continues, when the protocols of the wireless communication devices within the proximal region are of the like protocol, formatting a preamble of a frame of the wireless communication utilizing at least one of cyclic shifting of symbols, cyclic shifting of tones, sparse tone allocation, and sparse symbol allocation based on the number of transmit antennas.

Abstract: Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A means for decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations that need to be performed when updating edge messages, the calculations may be reduced to only performing product of terms functions. When implementing such functionality in hardware within a communication device that is operable to decode LDPC coded signals, this reduction in processing complexity greatly eases the actual hardware's complexity as well. A significant savings in processing resources, memory, memory management concerns, and other performance driving parameters may be made.