Abstract: A radio frequency identification (RFID) interface includes first coil, a plurality of coils, and a control module. The first coil is associated with an RFID tag and the plurality of coils is associated with an RFID reader. Each of the plurality of coils has a different orientation with respect to at least one axis of a multi-dimensional axis system. The control module is coupled to enable at least one of the plurality of coils based on electro-magnetic coupling between the first coil and the least one of the plurality of coils.

Abstract: A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

Abstract: An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

Abstract: A small form factor USB Bluetooth dongle includes a printed circuit board (PCB), a USB contact area, and a radio frequency (RF) transceiver die. The PCB includes a first primary surface and a second primary surface. The USB contact area is fabricated on the first primary surface. The RF transceiver die is mounted on the second primary surface, wherein the RF transceiver is in accordance with Bluetooth.

Abstract: Collecting traffic data regarding a plurality of wireless terminals includes periodically receiving Global Positioning System (GPS) location information from each of the plurality of wireless terminals by a location tracking server. For each of the plurality of wireless terminals, the location tracking server accumulates GPS location information. The location tracking server receives information regarding a geographic feature, processes the received GPS location information, and generates a traffic pattern report regarding the geographic feature based upon the accumulated GPS location information.

Abstract: An integrated circuit includes first, second and third circuits, a clock module and a rate adapting module. The first circuit causes frequency dependent noise and is clocked based on a clock signal. The second circuit is rate dependent and is clocked based on an operation dependent clock signal. The third circuit is susceptible to adverse performance when the frequency dependent noise has a component within a given frequency range. The clock module generates a clock signal having a rate such that frequency dependent noise components associated with the clock signal are outside the given frequency range. The rate adapting module is coupled to produce the operation dependent clock signal from the clock signal.

Abstract: In a digital communication infrastructure, intermediate network nodes compare packets from end-point devices with pluralities of virus templates. Upon detecting matches, virus service functions are invoked which interrupt the packet flow. Network wide template and service functionality updating is provided to service pluralities of virus service software vendors. Non-repetitive detection processing minimizes network load. Virus service functions may execute locally and/or remotely. Servicing may include dropping packets containing virus codes or, processing and routing the packets. Pop-up messages revealing underlying template matches are delivered with human challenge mechanism. The network nodes may be routers, packet switching exchanges, switches, access points, Internet service provider equipment, etc. External vendor servers and server clusters may assist network nodes in detecting and processing packets for virus codes.

Abstract: Virtual disk drive architecture. A novel approach is presented by which a virtual design system allows for the design, development, and testing of memory storage devices including hard disk drives (HDDs). A virtual disk drive architecture allows for the implementation and emulation of a full HDD system. All of the pieces of the HDD system (e.g., including both the read channel and the controller functionalities) are included and implemented to allow a designer to develop and test certain portions within the system. In some embodiments, one or more field programmable gate arrays (FPGAs) are employed to implement a hard drive (HD) controller in an all digital implementation. Various combinations including circuit boards and FPGAs can be employed to emulate an entire HDD system. In even other embodiments, one or more sockets, and appropriate interfacing, are included to allow the testing of actual chips within the virtual disk drive architecture.

Abstract: A video processing system captures a sequence of original video frames with a video camera, presents at least one frame of the sequence of original video frames on a video display, receives user input regarding the sequence of original video frames, and presents a sub-frame on the video display that corresponds to a region in at least one frame of the sequence of original video frames that is identified in the user input. The video processing system also generates metadata corresponding to the sub-frame, the metadata to be used by a target video player in modifying the sequence of original video frames to produce a full screen presentation on a target video display of the target video player corresponding to the sub-frame. Targeted sub-frame metadata can be specifically generated for use with a particular screen or screen size.

Abstract: A scheme in which a first decoder provides first decoding of a signal read from a disk. A second decoder, coupled to an output of the first decoder, combines with the first decoder to provide iterative decoding to recover data stored on the disk when in an iterative mode of operation. However, when in a non-iterative mode of operation, the output of the first decoder is coupled to an error correction code module to apply error correction code (ECC) to the output of the first decoder to recover data stored on the disk by non-iterative decoding.

Abstract: Video player circuitry used with encoded source video and a display. Decoder circuitry receives encoded source video and decodes the encoded source video to produce a sequence of full frames of video data. Pre-processing circuitry, pursuant to sub-frame information, generates a plurality of sequences of sub-frames of video data from the sequence of full frames of video data, a first sequence of the plurality of sequences of sub-frames of video data having a different center point within the sequence of full frames of video data than that of a second sequence of the plurality of sequences of sub-frames of video data. Post-processing circuitry, pursuant to supplemental information, modifies the plurality of sequences of sub-frames of video data to produce an output. Interface circuitry that delivers the output for subsequent presentation on the display.

Abstract: New version packet data devices support a backwards-compatible signal format. New version devices operate within a first frequency band while old version devices operate within a second frequency band. The first frequency band differs from but overlaps with the second frequency band. The new version devices may operate on a first carrier frequency (within the first frequency band) while old version devices may operate at a second carrier frequency (within the second frequency band). The new version devices and/or the old version devices may also support carrier-less modulations. Preamble, header, and trailer portions of a new version signal include a plurality of spectral copies of a baseband modulated signal. One or more of these spectral copies of the baseband modulated signal is/are indistinguishable from corresponding components of an old version signal. The payload of the new version signal may be formed in the same manner or may be formed in have a wider bandwidth, higher data rate format.

Abstract: A technique to sample a signal from a disk by using frequency and phase offset adjustment in a phase locked loop (PLL) timing recovery loop to sample read data from the disk, prior to a disk clocked clocking acquires a lock. Subsequently, sampling a signal from a disk by using only phase offset adjustment in the PLL timing recovery loop to sample read data from the disk after the disk clocked clocking acquires the lock. The sampled data is then error corrected by applying an error correction code (ECC).

Abstract: A technique to perform a guided partial response target search for characterizing a read channel of a disk drive. A target adaptation scheme pre-selects a plurality of targets from a pool of potential targets based on certain criteria and the selected targets are sorted in linear gradient orders. When target adaptation is being performed by comparing the equalizer output with an ideal reconstructed signal, a difference value sets a gradient vector that is used to determine which direction to move along the sorted list of targets to select the next target.

Abstract: A distribution server includes a communication interface, storage, and processing circuitry. The processing circuitry retrieves a full screen sequence of video and sub-frame metadata relating to the full screen sequence of video. The processing circuitry sub-frame processes the sequence of full screen video using the sub-frame metadata to produce a plurality of sub-frames of video. The processing circuitry assembles the plurality of sub-frames of video to produce an output sequence for a client system. The distribution server may also receive, store, and distribute the sub-frame metadata and/or the video for subsequent use by a video processing system.

Abstract: A receiver architecture for canceling blocking signals in the receive path includes a low noise amplifier for receiving and amplifying an inbound RF signal to produce an amplified inbound signal, in which the inbound RF signal includes a modulated RF signal and a blocking signal, and a cancellation module for substantially canceling the blocking signal from the amplified inbound RF signal and substantially passing the modulated RF signal. The cancellation module cancels the blocking signal by generating an injection signal representative of the blocking signal, combining the blocking signal with the injection signal to produce an error signal, updating the injection signal based on the error signal and using the injection signal to cancel the blocking signal from the amplified inbound RF signal.

Abstract: A video processing system applies sub-frame processing to video data to generate both a first sequence of sub-frames of video data and a second sequence of sub-frames of video data. The first sequence of sub-frames of video data and the second sequence of sub-frames of video data are defined by metadata. The processing circuitry generates a third sequence of sub-frames of video data by combining the first sequence of sub-frames of video data with the second sequence of sub-frames of video data. Adaptive video processing circuitry receives encoded source video data, raw source video data, similar display metadata, target display metadata, and/or target display information. The adaptive video processing circuitry processes its input information to produce one or more outputs that include tailored metadata, encoded target display video data, target display video data, and DRM/Billing Signaling.

Abstract: A removable storage media is received by and interacts with both a first video player system and a second video player system. The first video player system has a first video display that has a first display characteristic and the second video player system has a second video display that has a second display characteristic, the first display characteristic being different from the second display characteristic. The removable storage media includes a plurality of storage locations and stores a sequence of full frames of video data, first sub-frame metadata, and second sub-frame metadata. The first sub-frame metadata is generated and the second sub-frame metadata are used to process the full frames of video data to correspond to the first video display and the second video display, respectively.

Abstract: A controller is disclosed that can be used in controlling a drive device of a disk drive, or other systems, in the presence of sinusoidal disturbances. The controller includes a calibration module that generates a plurality of reference states for a reference region of a disk of the disk drive. An initialization state generation module generates a plurality of initialization states for at least one other region of the disk as a function of the plurality of reference states, a displacement between the other regions of the disk and the reference region of the disk, and a reference state transition matrix. A control module generates a control signal for the drive device based on the plurality of initialization states.

Abstract: A receiver architecture for canceling blocking signals in the receive path includes a low noise amplifier for receiving and amplifying an inbound RF signal to produce an amplified inbound signal, in which the inbound RF signal includes a modulated RF signal and a blocking signal, and a cancellation module for substantially canceling the blocking signal from the amplified inbound RF signal and substantially passing the modulated RF signal. The cancellation module cancels the blocking signal by generating an injection signal representative of the blocking signal, combining the blocking signal with the injection signal to produce an error signal, updating the injection signal based on the error signal and using the injection signal to cancel the blocking signal from the amplified inbound RF signal.