Abstract: A laptop that interacts with a television system. At least one module may be adapted to receive a user input identifying a video selection. The at least one module may also be adapted to display video information corresponding to the video selection. The at least one module may further be adapted to transmit a control signal adapted to cause the display of video information corresponding to the video selection on the television system. The laptop may, for example, be adapted to receive television system setting information and provide for user control of various television system settings. Also for example, the laptop may be adapted to receive media guide information, present such information to a user, provide for user selection of a media element, and transmit a control signal adapted to cause delivery of the selected media element from a multimedia source to the television system.

Abstract: An integrated circuit (IC) includes a baseband processing module, a disk driver interface, an RF section, and an interface module. The disk drive interface is coupled to the baseband processing module and to an off-IC disk drive, wherein the disk driver interface facilitates transfers between the baseband processing module and the off-IC disk drive.

Abstract: An system comprising an ingress device configured to receive and process data, wherein the ingress device comprises a plurality of processing stages configured to process the data, wherein a configurable subset of the stages comprises a selectable tap point, and wherein the ingress device is further configured to, upon reaching a selected tap point, suspend processing and send at least a portion of the data to another device; an offload engine device configured to receive data from the ingress device, after the selected tap point has been reached, and to provide additional processing of the data, which the ingress device is not configured to provide; an egress device configured to transmit the data that has been additionally processed by the offload engine device.

Abstract: A direct conversion tuner down-converts television signals, cable signals, or other signals directly from an RF frequency to an IF frequency and/or baseband, without an intermediate up-conversion step for image rejection. The direct conversion tuner includes a pre-select filter, an amplifier, an image reject mixer, and a poly-phase filter. The pre-select filter, amplifier, and the image reject mixer can be calibrated to provide sufficient image rejection to meet the NTSC requirements for TV signals. The entire direct conversion tuner can be fabricated on a single semiconductor substrate without requiring any off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

Abstract: A midspan power sourcing equipment (PSE) for operation with power over Ethernet (PoE). The midspan PSE provides powering over wire pairs that are also used for data communication. To ensure compatibility with legacy Ethernet devices, the ports used for transmission of data are designed to present an increased level of inductance.

Abstract: A multi-source data multiplexing system that accepts information packets from a plurality of signal sources, evaluates the relative efficiencies of data transmission, and transmits the information packets in provided grant regions for maximum efficiency. The multi-source data multiplexing system may accept any form of information packet from any form of signal source. The system receives a grant region, typically comprising a transmission time on a data channel, and inserts a information packet into the grant region. The actual information packet placed in the grant region may be one other than the packet for which the grant region was intended. Further, the multi-source data multiplexing system may fragment an information packet and transmit only a portion of the information packet in the grant region.

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.

Abstract: Methods and systems for level detector calibration are disclosed and may comprise calibrating a level detector integrated on-chip to eliminate an associated zero input offset voltage utilizing a replica bias circuit with no input ac voltage at the level detector or the replica bias circuit. The offset voltages of the level detector and the replica bias circuit may be combined to eliminate the associated zero input offset voltage of the level detector. The output signal may be generated by a difference of output signals from the level detector and the replica bias circuit. The level detector and the replica bias circuit may be biased utilizing a similar bias voltage. A plurality of known input voltages may be utilized to generate a corresponding plurality of output voltages of the level detector, generating a corrected transfer function that may be used to accurately set a transmitter power level.

Abstract: A method and system for combining requests for data bandwidth by a data source for transmission of data over a wireless communication medium is provided. A central node receives one or more bandwidth requests from one or more data sources via wireless communication. A scheduler then combines one or more bandwidths requests from the same data source to create a single data burst bandwidth. The central node then grants the data burst bandwidth to the appropriate data source via wireless communication.

Abstract: Aspects of a method and system for extending dynamic range of an RF signal are provided. In this regard, a signal representative of an amplitude of a pair of baseband signals may be generated. The amplitude of the generated signal may be expanded, and the amplitude of the baseband signals may be compressed. In this regard, the compression and the expansion may be inverse functions of each other. Additionally, the compressed baseband signals may be combined to generate an intermediate signal which may be amplitude modulated by the expanded signal. The amplitude modulation may result from controlling a gain, a voltage source, and/or a current source of a power amplifier. The intermediate signal may be generated by up-converting the baseband signals and subsequently combining the up-converted signals.

Abstract: A data communication system capable of forwarding IP-addressed data to devices as such devices move among networks having different IP addresses is disclosed herein. The system includes first and second networks containing first and second pluralities of nodes. At least one of the first plurality of nodes is adapted to receive data transmissions from an external IP-based network. Upon joining the first network, this device is assigned an IP address which remains with it irrespective of whether it moves beyond the range of the first network. When this device roams into the vicinity of the second network, data addressed to the device which is received at the first network is forwarded via at least one node of the second network to the roaming device.

Abstract: The present invention relates to battery chargers. A first controller can be configured to set, when a first power supply is coupled to a first port, a current produced by a variable current source at a safe rate to charge a battery. An ammeter can be configured to measure, when the battery is coupled to a second port, the current flowing into the battery. The first controller can be configured to increase, after a passing of a quantifiable amount of time, the current produced by the variable current source by a quantifiable amount of current. The first controller can be configured to continue iteratively to increase, after the passing of the quantifiable amount of time, the current produced by the variable current source by the quantifiable amount of current until the safe rate is near or at a highest safe rate to charge the battery.

Abstract: A network device for processing a packet can have at least one port within the network device configured to received or transmit a packet, and a storage unit configured to store a port bit map, wherein the port bit map corresponds to the at least one port. Furthermore, the network device for processing a packet can have a rules table configured to have at least one port match entry and at least one action corresponding to the at least one port match entry therein, and a control unit configured to compare the port bit map with the at least one port match entry, and to implement the at least one action when a first positive value results from comparing the port bit map with the port match entry.

Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Abstract: A system for processing radio frequency (RF) signals includes a searcher and a plurality of Cluster Path Processor (CPPs). The searcher detects a maximum signal energy level and position of at least one of a plurality of individual distinct path signals in a signal cluster of a first information signal, wherein at least a portion of the plurality of individual distinct path signals is received within a duration of a corresponding delay spread. The sampling position is used as a starting sampling location by the plurality of CPPs, including a first information signal CPP and a second information signal CPP. Fine sampling positions of the plurality of CPPs are based upon channel energy estimates for the plurality of individual distinct path signals. CPP outputs are employed to produce channel estimates, which are themselves used in subsequent equalization operations. Sampling positions may change over time in order to satisfy alignment criteria.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically.

Abstract: Methods, systems and computer program products to implement hardware memory locks are described herein. A system to implement hardware memory locks is provided. The system comprises an off-chip memory coupled to a System-On-a-Chip(SOC) unit that includes a controller and an on-chip memory. Upon receiving a request from a requester to access a first memory location in the off-chip memory, the controller is enabled to grant access to modify the first memory location based on an entry stored in a second memory location of the on-chip memory. In an embodiment, the on-chip memory is Static Random Access Memory (SRAM) and the off-chip memory is Random Access Memory (RAM).

Abstract: A method of mediating the flow of datagrams to a destination in a network is disclosed. The method includes the steps of receiving a datagram at a port of a network device, evaluating a destination address for the datagram based on fields in the incoming packet, searching a longest prefix match (LPM) table using the destination address as a LPM key, determining an address table index and an offset based on entries found in the search of the longest prefix match table, searching an address table using the address table index and the offset as an address key to determine an egress port number of the network device and forwarding the packet based upon at least the egress port number.

Abstract: An apparatus comprising a plurality of fixed logic circuits, wherein each of the fixed logic circuits is configured to receive a plurality of input signals, perform combinational logic operations using the input signals, and produce at least one output signal, and wherein the combinational logic operations are substantially fixed; and a programmable logic core configured to functionally replace a selected subset of the plurality of fixed logic circuits, receive the input signals of the selected subset of the plurality of fixed logic circuits, perform logic operations on the input signals, and produce at least one output signal as the output signal of the selected subset of the plurality of fixed logic circuits, and wherein the logic operations are dynamically changeable.

Abstract: A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.