Abstract: A memory system is provided comprising a memory controller, a level 1 (L1) cache including L1 tag memory and L1 data memory, a level 2 (L2) cache coupled to the L1 cache, the L2 cache including L2 tag memory having a plurality of L2 tag entries and a L2 data memory having a plurality of L2 data entries. The L2 tag entries are more than the L2 data entries. In response to receiving a tag and an associated data, if L2 tag entries having corresponding L2 data entries are unavailable and if a first tag in a first L2 tag entry with an associated first data in a first L2 data entry has a more recent or duplicate value of the first data in the L1 data memory, the memory controller moves the first tag to a second L2 tag entry that does not have a corresponding L2 data entry, vacates the first L2 tag entry and the first L2 data entry and stores the received tag in the first L2 tag entry and the received data in the first L2 data entry.

Abstract: A sigma-delta digital to analog converter (DAC) module converts the digital input signal to the analog output signal through segmentation, including a primary and a secondary sigma-delta modulator. The primary sigma-delta modulator produces a primary digital segment and a primary quantization error. A primary sample is delayed, decoded, scrambled and converted to produce a primary analog segment. A secondary sigma-delta modulates the primary quantization error to produce a secondary digital segment which is noise shaped by a noise transfer function of the primary sigma-delta modulator to produce a noise shaped secondary digital segment which is decoded, scrambled, converted and scaled to produce a secondary analog segment. An adder combines the primary analog segment and the secondary analog segment to produce the analog output signal.

Abstract: A system and method that provide dynamic reconfiguration of communication resources in a multi-transceiver configuration. Various aspects of the present invention may comprise communicating a first portion of a first communication using a plurality of transceivers. A determination may be made to reallocate at least one of the plurality of transceivers for a second communication. A second portion of the first communication may be communicated using the plurality of transceivers less the reallocated transceiver(s), and the second communication may be communicated using at least the reallocated transceiver(s). Various aspects of the present invention may also comprise communicating a first communication utilizing a first transceiver and a second communication utilizing a second transceiver. A determination may be made to utilize the first and second transceivers in a MIMO configuration to communicate next information.

Abstract: There is provided a method of managing power utilization for use by a first communication system having a first communication mode and a second communication mode, for communication over a PHY connection through a cable connecting the two systems. The method comprises establishing the PHY connection with the second communication system, detecting interoperability of the two systems in the first communication mode, determining a length of the cable connecting the first communication system to the second communication system, selecting a mode based on the length of the cable, if the detecting detects interoperability of the first communication system and the second communication system in the first communication mode, selecting the second communication mode as the mode, if the detecting does not detect interoperability of the first communication system and the second communication system in the first communication mode, communicating data using the PHY connection through the cable in the mode.

Abstract: A system and method for removing impulsive noise from a digital signal are disclosed. The system and method determines either a neighborhood maximum and/or a neighborhood minimum for a pixel of interest. The intensity of the pixel of interest is then compared to the neighborhood maximum or the neighborhood minimum to determine whether the pixel of interest should be replaced.

Abstract: Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Abstract: A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of network switches. A module id bitmap of the incoming data packet is resolved and a bit corresponding to the first switch of the module id bitmap is examined to determine if the bit is set. A destination address of the incoming data packet is resolved when the corresponding bit is set and the incoming data packet is forwarded or dropped based on the destination address. When the corresponding bit is not set, the incoming data packet is forwarded to a next switch of the series of network switches. A network switch configured to allow for cascading of data packets is also disclosed.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: A method and system are provided for synthesizing a corrupted frame output from a decoder including one or more predictive filters. The corrupted frame is representative of one segment of a decoded signal output from the decoder. The method comprises extrapolating a replacement frame based upon another segment of the decoded signal and substituting the replacement frame for the corrupted frame. Finally, the internal states of the filters are updated based upon the substituting.

Abstract: A communication network having at least one access point supports wireless communication among a plurality of wireless roaming devices via a first and a second wireless channel. The access point comprises a first and a second transceiver. The first and second transceivers operate on the first and second wireless channels, respectively. Each of the plurality of wireless roaming devices are capable of communicating on the first and second wireless channel. In one embodiment, the first wireless channel is used to exchange data, while the second channel is used to manage such exchanges as well as access to the first channel. In an alternate embodiment, both channels are used to support communication flow, however the first channel supports a protocol that is more deterministic than that of the second channel. Allocation of ones of the plurality of wireless roaming devices from one channel to the next may occur per direction from the access point.

Abstract: Methods and apparatus for providing a local oscillator (LO) signal are disclosed. An example apparatus includes a circuit for providing the LO signal. The circuit includes a voltage controlled oscillator (VCO) that is configured to operate at a first supply voltage. The VCO is also configured to produce a VCO signal. The circuit also includes an LO generator that is coupled with the VCO so as to receive the VCO signal. In the example apparatus, the LO generator is configured to operate at a second supply voltage, where the second supply voltage is greater than the first supply voltage. Further, the LO generator includes one or more resistively loaded circuits for producing the LO signal from the VCO signal.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: An apparatus and method for multi-point detection in a power source equipment (PSE) device is provided. During multi-point detection, a series of at least four currents is sequentially applied to a link port of the PSE device. Each current is applied during a different measurement interval. A voltage measurement sample is obtained for each of the measurement intervals. A difference in voltage between alternating voltage samples is determined and used by a detection module to determine whether a valid power device is coupled to the link port of the PSE.

Abstract: A method for generating a preamble of an Orthogonal Frequency Division Multiplexed (OFDM) data frame for a multiple input multiple output (MIMO) wireless communication includes determining at least one system condition preamble format parameter. When the system condition preamble format parameter satisfies a first preamble format parameter a preamble having a first preamble format is formed. When the system condition preamble format parameter satisfies a second preamble format parameter, a preamble having a second preamble format is formed. Further, when the system condition preamble format parameter satisfies a third preamble format parameter, a preamble having a third preamble format is formed. The first, second, and third preamble formats differ based upon their lengths, fields, and modulation formats of a high throughput signal field.

Abstract: Data packets transmitted over a wireless network are suppressed by hardware at the transmitting end and expanded on the receiving end. This conserves bandwidth as well as reduces the processing resource requirements in both the subscriber station and the base station. An extended header element is added to a data packet that is to be transmitted over the wireless network. The extended header element contains an index that is used along with an identifier to access a rule. The rule is used to determine which bytes are to be suppressed at the transmitter and expanded at the receiver.

Abstract: A power amplifier circuit including a first transistor, a second transistor, and a power control circuit. The first transistor includes a first input and a first output. The second transistor includes a second input coupled in series with the first output of the first transistor. The input circuit is coupled to the first input of the first transistor. The power control circuit is coupled to the second input of the second transistor. The control circuit includes a time delay circuit and a variable source.

Abstract: Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.

Abstract: A system for adding a time stamp to transmission traffic on a wireless network comprises a front end processor that receives a packet from the network and generates a Start Of Frame pulse and a LENGTH field corresponding to a length of the packet. A time stamp generator generates a time stamp by sampling the system master time counter. A synchronizer receives the SOF pulse and the LENGTH field from the front end processor, and generates a control signal. A multiplexer inputs the packet from the front end processor, the control signal and the time stamp, and outputs a modified packet with a field in the packet replaced by the time stamp.

Abstract: A system and method for global power management in a power over Ethernet (PoE) chassis. Power supply status signals indicative of an operating condition of a plurality of power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips in a plurality of blades of a chassis system. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of power supplies into a powering decision for each of the ports served by the PSE controller chip. Global power management is also effected through the use of scaling factors for the various blades to ensure that the lowest priority powered port (LPPP) in a first blade does not have a lower priority than the highest priority non-powered port (HPNPP) in a second blade.