Abstract: An FFT butterfly instruction based on single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform FFT butterfly operations. The FFT butterfly instruction can implement one or more instances of the FFT butterfly operation (e.g., non-SIMD, 2-way SIMD, 4-way SIMD, etc.), at once, each instance operating over a set of complex values. A control register or variant opcode controls the behavior of the FFT butterfly operation. The contents of the control register or the variant opcode can be altered to configure the butterfly behavior to suit specific circumstances. The FFT butterfly instruction can be used in the software on a processor in a chip-set implementing the central-office modem end of a DSL link. The FFT butterfly instruction can also be used in other contexts where an FFT function is performed (and/or where an FFT butterfly operation is used) including systems that do not implement DSL or DMT.

Abstract: A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Abstract: Partial-parallel implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which a selected number of cycles is performed during each of bit node processing and check node processing when performing error correction decoding of an LDPC coded signal. The number of cycles of each of bit node processing and check node processing need not be the same. At least one functional block, component, portion of hardware, or calculation can be used during both of the bit node processing and check node processing thereby conserving space with an efficient use of processing resources. At a minimum, a semi-parallel approach can be performed where 2 cycles are performed during each of bit node processing and check node processing. Alternatively, more than 2 cycles can be performed for each of bit node processing and check node processing.

Abstract: Clocking Chien searching at different frequency than other Reed-Solomon (RS) ECC decoding functions. An efficient implementation allows for a fast clock signal to govern the operation of the more computationally and time-intensive portions of the error correction code (ECC) time budget. For example, at least one module and/or decoding function within the ECC decoding is governed by using a first clock signal, and at least one other module and/or decoding function (or all the other modules and/or decoding functions) is/are governed by using a second clock signal. In one implementation of Reed-Solomon (RS) decoding, the Chien searching function is operated using a faster clock signal than at least one other RS error correction decoding function thereby allowing for a significant reduction in area and power than other architectural trade-offs.

Abstract: Aspects of a method and system for polar modulating OFDM signals with discontinuous phase may include amplifying an OFDM signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain and/or the amplitude offset gain may be adjusted dynamically and/or adaptively.

Abstract: A system and method for detecting PES headers is presented herein. PES headers are detected by a combination of hardware and firmware. Hardware logic is used to detect the PES start codes while multithreaded firmware us used to process the packet.

Abstract: In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified. If the maximum value exceeds a threshold, it will be declared as a peak and the address associated is the peak timing.

Abstract: The present invention is directed to an improved memory and I/O bridge that provides an improved interface for communicating data between the data bus of the system processor and the memory controller. The memory and I/O bus bridge according to the present invention provides increased performance in the system. The memory and I/O bridge can include a deep memory access request FIFO to queue up memory access requests when the memory controller is busy. The memory and I/O bridge can include a memory write data buffer for holding and merging memory write operations to the same page of memory. The memory and I/O bridge can include a memory read data buffer for holding and queuing data and instructions read from memory, waiting to be forward to the data bus. The memory data read buffer can operate in one or more software selectable prefetch modes, which can cause one or more pages to be read in response to a single memory read instruction.

Abstract: A programmable attenuator includes a resistor ladder having a plurality of taps to provide a coarse gain control. Coupled to each tap is a plurality of switches. Control logic activates or deactivates individual switches in the plurality of switches to provide a fine gain control. More specifically, a set of activated switches provides fine gain control by determining an overall attenuation level interpolated between an adjacent pair of taps.

Abstract: A circuit and method to reduce jitter and/or noise in a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) control signal is tapped and filtered to create a low-noise, filtered VCO control signal. The filtered and unfiltered control signals are individually weighted and then combined to create a modified VCO control signal which reduces the jitter and/or the noise by reducing an effect of VCO gain on the jitter and/or the noise.

Abstract: In the current invention, an apparatus, method, and computer program product for allocating a contiguous area of memory from a repository are provided. In accordance with an embodiment of the invention, a repository pointer to a contiguous set of data blocks in the repository and a system pointer operable to point to the contiguous set of data blocks are allocated. The value of the repository pointer is subsequently assigned to the system pointer.

Abstract: Discrete multitone transmission assigns bits to tones for transmission. The bits are assigned using permutations of bits and tones that cycle through a sequence of permutations in successive frames.

Abstract: A method of communicating data to a receiving antenna from N transmitting antennas, where N is an integer, includes the steps of determining whether a legacy transmission mode has been selected, producing N data streams from outbound data, and applying the N data streams to a space/time encoder to produce N encoded signals. When the legacy transmission mode has not been selected, the N encoded signals are transmitting from N transmitting antennas and when the legacy transmission mode has been selected, the one encoded signal is transmitted from one of the N transmitting antennas. The legacy transmission mode allows receivers to receive and process transmitted signals when the receivers are only configured to receive the transmitted signals from a single transmitting antenna.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: Managing packet data network jitter is disclosed. A first call data associated with a mobile network communication session is received. A second call data that is older than the first call data is dropped from a buffer if required to make room in the buffer for the first call data.

Abstract: An apparatus may include a flow cache module that is arranged and configured to derive, at runtime, a custom sequence of code segments for packets belonging to a specific connection using a first packet of the specific connection and a parser module that is arranged and configured to identify packets as belonging to the specific connection using an Internet Protocol (IP) tuple of the packets, where the flow cache module is arranged and configured to apply the custom sequence of code segments to the identified packets.

Abstract: According to an example embodiment, an apparatus may include a client device including a processor and memory. The client device may be configured to obtain, via a secure communication, a certificate identifying a publically accessible wireless access point (AP) and a public key for the AP, the AP being publically accessible. The client (or client device) may be configured to generate a challenge, send the challenge to the AP, wherein the AP has a private key securely stored in a hardware security module of the AP. The private key may correspond to the public key for the AP. The client may be configured to receive a response from the AP, the response being generated by the AP based on the challenge and the private key for the AP, and authenticate the AP based on the response.

Abstract: Systems and methods for performing a method for reducing power consumption in MoCA devices that are connected via a coax network are provided. One method according to the invention includes, in a home network having a plurality of network modules, one of said plurality of network modules being a network controller, each of said plurality of network modules being connected to a coax backbone, communicating over the coax backbone between the plurality of network modules. The method further includes using the master module to receive requests sent over the coax backbone from the plurality of network modules for bandwidth to transmit bursts. The master module may establish an order of transmission opportunities for the plurality of network modules to follow when transmitting bursts directly to other network modules via the coax backbone. The method may also include using the master module to toggle each of the networked modules between a running power state and a standby power state.

Abstract: An integrated circuit package is provided. The integrated circuit package includes a heat sink, a cured silicone thermally conductive adhesive material, and a surface. The adhesive material attaches the heat sink to the surface. The surface is a surface of at least one of a substrate, a surface of an integrated circuit die, or a surface of an encapsulating material of the integrated circuit package.

Abstract: A system and method for changing retransmission and rescheduling queues to support retransmission in a communications system is presented. A method for changing queue size values includes, for an increase in data rate, determining a new retransmission queue size value for a retransmission queue at the transmitting device and a new rescheduling queue size value for a rescheduling queue at the receiving device such that an amount of time for a DTU to enter and exit the retransmission queue is greater than a roundtrip delay. For a decrease in data rate, the method includes determining the new retransmission queue size value and the new rescheduling queue size value such that an amount of time for a DTU to enter and exit the retransmission queue is less than a maximum delay. Systems and methods for changing the retransmission and rescheduling queue sizes are also presented.