Abstract: Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: frequency translating an inphase component of the first signal utilizing a filtered fast-switching oscillating signal generated using at least a direct digital frequency synthesizer (DDFS), and frequency translating a corresponding quadrature component of the first signal utilizing a phase-shifted version of the generated and filtered fast-switching oscillating signal. The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively.

Abstract: Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.

Abstract: A device includes an on-chip gyrating circuit that generates a motion parameter based on motion of the device. An RF transceiver generates an outbound RF signal from an outbound symbol stream, transmits the outbound RF signal to a remote station of a wireless network, and generates an inbound symbol stream from an inbound RF signal received from the at least one remote station. A processing module is coupled to process the motion parameter to produce motion data, to convert outbound data into the outbound symbol stream, and to convert the inbound symbol stream into inbound data, wherein the outbound data includes the motion data.

Abstract: The invention provides a system and method for updating software in the CPU of a network device without interrupting the operation of the network device. The invention determines whether operating state information is recoverable. If it is not recoverable, then it will be stored in a metadata module or reload buffer. When the CPU is rebooted, after a software update or crash, it operates in a special reload mode and is able to recover any system state information not available in the network device from the metadata module.

Abstract: A token-based receiver diversity processing is described. In one embodiment, a receiver diversity comprises repeaters receiving wirelessly transmitted packets from a mobile station, and one of the repeaters forwarding packets of the wirelessly transmitted packets to a switch if the one repeater is currently assigned to forward packets from the mobile station based on an indicator assigned prior to the wirelessly transmitted packets being sent.

Abstract: A high speed isolation interface which can be used to enable high speed communications between the isolated side and the wire side in a PoE system is provided. The high speed isolation interface may implement an Ethernet or non-Ethernet based signaling scheme. The high speed isolation interface can be used within both PSE (endspan or midspan) and PD systems, including single port and multi-port PSE and PD systems. Further, the high speed isolation interface is usable within pre-standard PoE, 802.3af PoE, and 802.3at PoE systems. The high speed isolation interface may also be used within 2-pair PoE (Alternative A) and 4-pair PoE (Alternative B) systems.

Abstract: A multimode communication device with a shared signal path programmable filter and a method for utilizing a shared signal path programmable filter in a multimode communication device. Various aspects of the present invention comprise a first module adapted to receive a first communication signal (e.g., corresponding to a first communication protocol) and a second module adapted to receive a second communication signal (e.g., corresponding to a second communication protocol). A shared filter, communicatively coupled to the first and second modules, may be adapted to filter the first and/or second communication signals in accordance with a plurality of selectable sets of filter response characteristics (e.g., associated with the first and second communication protocols). A filter control module may be adapted to select a set of filter response characteristics from a plurality of such sets and program the shared filter to filter a communication signal in accordance with the selected set.

Abstract: The motherboard comprises a CPU and a memory component; further at least one video data processing chip mounted to the motherboard wherein the video data processing chip is programmable; and further at least one additional memory component provided to store a software that is executable by the video data processing chip.

Abstract: A system and method for dynamically reducing the precision of datapath modules within an FFT unit without adversely affecting the demodulation of an orthogonal frequency division multiplexing (OFDM) signal. An FFT unit is typically implemented in an OFDM receiver to separate sub-carriers within a received OFDM signal. In general, an FFT unit implemented within an OFDM receiver must be designed to operate with a precision high enough such that quantization noise, introduced within the FFT unit, does not dominate the overall maximum SNR requirement of the system. However, the SNR requirement for many OFDM receivers is dynamic and, as a result, OFDM receivers often have an instantaneous SNR requirement far below the required maximum. In these situations, it would be advantageous to reduce the precision of datapath modules within the FFT to conserve power, which is often limited in wireless devices.

Abstract: A system and method for regulating power consumption within an integrated circuit (IC) with a modular design. The IC is designed so that any one distinct functional module within the IC utilizes only transistors with a substantially same or similar critical voltage level, which may for example be the threshold voltage of the transistors. Consequently, the supply voltage delivered to each functional modules can be lowered to the minimum voltage necessary to enable the transistors within the module to operate. Similarly, modules within the IC may be designed with transistors which share a common value for a substrate bias voltage or a clock speed, or with a combination of common values for several electrical factors. In this way, it is possible to reduce power consumption by fine-tuning the voltages supplied to (or clock speeds driving) specific modules, in a way which is custom-tuned to each module.

Abstract: A transmitter includes a detection element to determine when a current power requirement of a communication link is less than the standard transmit power. The current power requirement may be determined by a current operation condition of the communication link, for instance. The transmit power of the transmitter may be set to be less than the standard power in any of a variety of ways. For example, a center tap voltage of the transmitter may be reduced. In another example, a class of operation of the transmitter may be changed. In yet another example, the transmitter may include a current mirror having a plurality of diode-connected transistors coupled in parallel, thereby reducing the current at output terminals of the transmitter. Reducing the current at the output terminals decreases the output power of the transmitter, which may reduce the power consumed by the transmitter.

Abstract: A network switch for switching packets from a source to a destination includes a source port for receiving an incoming packet from a source, a destination port that contains a path to a destination for the packet, and a programmable counter unit for counting a number of packets of selected packet types which are received by the switch.

Abstract: In an RF communication system, aspects for diversity processing may comprise processing a plurality of received multipath signals as clusters of signals. The received multipath signals may be diversity signals received from diversity transmit antennas at a base station. Timing information may be generated for tracking the clusters of signals. Complex phase and amplitude information may also be estimated for at least some of the multipath signals in the clusters of signals. At least a portion of the received multipath signals may be combined to form a single path processed diversity signal. A plurality of the single path processed diversity signals may be combined together, where each of the single path processed diversity signals may be derived from one of the plurality of diversity transmit antennas at the base station. The diversity signals may be transmitted via at least one of a plurality of diversity modes.

Abstract: A system for adding a time stamp to transmission traffic on a wireless network comprises a front end processor that receives a packet from the network and generates a Start Of Frame pulse and a LENGTH field corresponding to a length of the packet. A time stamp generator generates a time stamp by sampling the system master time counter. A synchronizer receives the SOF pulse and the LENGTH field from the front end processor, and generates a control signal. A multiplexer inputs the packet from the front end processor, the control signal and the time stamp, and outputs a modified packet with a field in the packet replaced by the time stamp.

Abstract: A system and method are provided allowing for successive approximation analog to digital conversion. A first differential voltage is sampled and held during a first cycle. The first differential voltage is converted to a differential current. A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances. First and second portions of the second differential voltage are compared to produce a comparison result therefrom. Successive approximation is used to generate a signal based on the comparison result, the signal being an output signal and being used to control resistances of respective ones of the first and second variable resistances during subsequent cycles.

Abstract: A novel means for performing dibit extraction is presented. Any one of an unequalized signal dibit, equalized signal dibit, or noise dibit can be extracted. Instead of using the correlation properties of a PN (Pseudo-Noise) sequence to approximate a PN deconvolution sequence, the use of the actual deconvolution sequence (i.e., PN sequence that includes values of +k and 0, where k is oftentimes 1) is employed so that no approximations are needed. The resulting estimate of the channel is therefore very accurate.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

Abstract: Methods and systems are provided that use smartcards, such as subscriber identity module (SIM) cards to provide secure functions for a mobile client. One embodiment of the invention provides a mobile communication network system that includes a mobile network, a mobile terminal, a server coupled to the mobile terminal via the mobile network, and a subscriber identity module (SIM) card coupled to the mobile terminal. The SIM card includes a first key and a second key. The first key is used to authenticate an intended user of the mobile terminal to the mobile network. Upon successful authentication of the intended user to the mobile network, the mobile terminal downloads a function offered from the server through the mobile network. The second key is then used by the mobile terminal to authenticate the intended user to the downloaded function so that the intended user can utilize the function.

Abstract: Aspects of a method and system for parsing bits in an interleaver for adaptive modulations in a multiple input multiple output (MIMO) wireless local area network (WLAN) system are provided. The interleaver may assign at least one binary bit of information, among a plurality of binary bits of information to be transmitted, to one of a plurality of spatial streams based on a current modulation type. A subsequent binary bit of information, among a plurality of binary bits of information to be transmitted, may be assigned to a subsequent one of the plurality of spatial streams based on the current modulation type and/or a subsequent modulation type. The interleaver may assign at least one additional bit of information, among the plurality of binary bits of information to be transmitted, to one of a plurality of spatial streams based on the current modulation type and/or the subsequent modulation type.