Abstract: A method to eliminate discontinuities in an adaptively filtered signal includes filtering a beginning portion of a current signal frame using a past set of filter coefficients, thereby producing a first filtered frame portion. The method also includes filtering the beginning portion of the current signal frame using a current set of filter coefficients, thereby producing a second filtered frame portion. The method also includes modifying the second filtered frame portion with the first filtered frame portion so as to smooth a possible filtered signal discontinuity between the second filtered frame portion and a past filtered frame produced using the past filter coefficients.

Abstract: In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets.

Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay.

Abstract: A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory.

Abstract: A method of performing an excitation Vector Quantization (VQ) in a Noise Feedback Coding environment involves reorganizing a calculation of an energy of an error vector for each of a plurality of candidate excitation vectors of a codebook. The energy of the error vector is a cost function that is minimized during a search of the codebook for a best candidate excitation VQ vector. The reorganization includes expanding a Mean Squared Error (MSE) term of the error vector, excluding an energy term that is invariant to the candidate excitation vector, and pre-computing energy terms of ZERO-STATE responses of the candidate excitation vectors that are invariant to sub-vectors of a subframe. Another method searches a signed codebook. Both methods use correlation techniques.

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A quantizer for quantization of a vector comprises a codevector generator that generates a set of candidate codevectors and a memory for storing an illegal space definition representing illegal vectors. The quantizer also includes a legal status tester that determines legal candidate codevectors among the set of candidate codevectors using the illegal space definition, and a codevector selector that determines a best legal candidate codevector among the one or more legal candidate codevectors. The vector includes parameters relating to a speech and/or audio signal, such as Line Spectral Frequencies (LSFs).

Abstract: A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value.

Abstract: A system and method for providing a sort in a computer system is disclosed. The sort is based on a plurality of values of a key. Each of the plurality of items has an associated value of the plurality of values. The method and system include providing a new item of the plurality of items to a plurality of sort cells. The new item includes a new value of the plurality of values. The plurality of sort cells is for sorting the plurality of items. Each sort cell is for sorting a corresponding item of the plurality of items. The corresponding item has a corresponding value of the plurality of values. The method and system further include comparing the new value to the corresponding value for each of the plurality of sort cells to determine whether to retain the corresponding item. Each of the plurality of sort cells retains the corresponding item if the corresponding item is to be retained.

Abstract: A method of searching a signed codebook to quantize a vector includes weighting a shape codevector in a set of shape codevectors with a weighting function for a Weighted Mean Square Error (WMSE) criteria, to produce a weighted shape codevector. The method further includes correlating the weighted shape codevector with the vector to produce a weighted correlation term. The method also includes determining, based on a sign of the weighted correlation term, a preferred one of a positive and a negative signed codevector associated with the shape codevector. The method further includes determining whether one of the signed codevectors does not belong to an illegal space defining illegal vectors.

Abstract: A method and system are provided for synthesizing a number of corrupted frames output from a decoder including one or more predictive filters. The corrupted frames are representative of one segment of a decoded signal (sq(n)) output from the decoder. The method comprises determining a first preliminary time lag (ppfe1) based upon examining a predetermined number (K) of samples of another segment of the decoded signal and determining a scaling factor (ptfe) associated with the examined number (K) of samples when the first preliminary time lag (ppfe1) is determined. The method also comprises extrapolating one or more replacement frames based upon the first preliminary time lag (ppfe1) and the scaling factor (ptfe).

Abstract: A transceiver includes a Downstream Signal Processor (DSP), an Upstream Signal Processor (USP), a Local Oscillator (LO), a differencer, a reference signal generator, and an estimator. The DSP receives an initial downstream signal, a downstream LO signal from the LO, and from the estimator a frequency-offset estimate indicative of a free-running frequency offset included in the initial downstream signal. The DSP uses the LO signal and the estimate to frequency down-convert the initial downstream signal, and also to remove the frequency offset from the initial downstream signal, thereby producing a corrected downstream signal. The USP uses both an upstream LO signal from the LO and the estimate to frequency convert an initial upstream signal so as to produce a frequency pre-corrected upstream signal.

Abstract: The present invention is drawn to a network device configured to prevent data misalignment of a data packet containing extra header bytes. The network device includes an ingress module having an input interface to receive data. A header detector configured to detect the header bytes of the cell and remove the header from the cell of the data packet is also provided on the network device. A counter determines whether the cell of the data packet contains a multiple of a predetermined bytes. If the counter determines that the cell of the data packet does not satisfy the multiple of the predetermined bytes, an insertion module inserts null bytes into the cell of the data packet to form a modified cell of the data packet. Then, an extraction module removes the null bytes from the modified cell of the data packet when the modified cell exits the network device.

Abstract: A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a continuing interconnection coupled to the first and second spiral conductive patterns; an interface coupled to the first and second spiral conductive patterns; and a conductive shield pattern disposed on a third surface that is adjacent to the second surface. The interface includes a first terminal disposed on the first surface that is coupled to the first spiral conductive pattern. The interface also includes a second terminal that is disposed on the first surface and coupled to said second spiral conductive pattern.

Abstract: Methods and circuitry reduce adverse impacts of intermodulation and optimize performance of integrated circuits that include two or more oscillator circuits on the same chip. In one embodiment, intermodulation between voltage-controlled oscillators (VCOs)in the receiver and transmitter paths of a transceiver is reduced by adjusting relative power of the VCOs and/or bandwidths of the phase-locked loops (PLLs). The invention measures the injection lock frequency range of the VCOs based on which transmitter and receiver VCO power and loop bandwidths are adjusted.

Abstract: A sub-quantizer for sub-quantization of a vector includes a sub-codevector generator that generates a set of candidate sub-codevectors, and transformation logic that transforms each candidate sub-codevector into a corresponding codevector. A memory stores an illegal space definition representing illegal vectors. A legal status tester determines legal codevectors among the codevectors based on the illegal space definition. An error calculator generates error terms corresponding to the candidate sub-codevector, and a sub-codevector selector determines a best one of the sub-codevectors corresponding to a legal codevector and a best error term. The vector includes parameters relating to a speech and/or audio signal, such as Line Spectral Frequencies (LSFs).

Abstract: A device of dynamic communication of information allows, on the average, non-integer bits per symbol transmission, using a compact code set or a partial response decoding receiver. A stream of k or k+1 data bits is grouped into bit vectors which then are mapped onto corresponding signal constellations forming transmission symbols. Two or more symbols can be grouped and further encoded, so that a symbol is spread across the two or more symbols being communicated. Sequence estimation using, for example, maximum likelihood techniques, as informed by noise estimates relative to the received signal. Each branch metric in computing the path metric of a considered sequence at the receiver is weighted by the inverse of the noise power. It is desirable that the constellation selection, sequence estimation and noise estimation be performed continuously and dynamically.

Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. A multiple context processing element is configured to store a number of configuration memory contexts. This multiple context processing element maintains data of a current configuration. State information is received from at least one other multiple context processing element. At least one configuration control signal is generated in responses to the state information and the data of a current configuration. One of multiple configuration memory contexts is selected in response to the configuration control signal, the selected configuration memory context controlling the multiple context processing element. Each multiple context processing element in the networked array of multiple context processing elements has an assigned physical and virtual identification.

Abstract: A point-to-multipoint network interface is provided that is simpler and less costly to implement than conventional Ethernet switches. The interface includes a plurality of downstream transmitters for transmitting data packets to a plurality of end user devices, a plurality of downstream receivers for receiving data packets from the plurality of end user devices, an upstream transmitter and an upstream receiver. A multiplexer within the interface multiplexes data packets received from the end user devices into a stream of data packets for transmission to a higher level node regardless of the destination address of the data packets. Conversely, a demultiplexer within the interface demultiplexes a stream of data packets received from the higher level node into individual data packets for selective transmission to one of the plurality of end user devices. The interface can support asymmetrical transmission rates on the upstream and downstream channels between the interface and the end user devices.