Abstract: An active splitter circuit arrangement includes a first amplification module having a number of first input ports and first output ports. The first amplification module is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals, each substantially matching the input signal. Also included is a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports. The first gain control device is configured to control a gain of the first amplification module. Next, a number of second amplification modules corresponding to the number of output signals has a number of second input ports respectively coupled to the first output ports.

Abstract: Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal and a differential input signal as a circuit input. A differential amplifier drive signal is produced in response to the received supply voltage signal, the received differential input signal, and the received differential control signal. The received differential input signal is adjusted to a value where magnitudes of negative and positive components of the differential control signal become equal to one another and are within a predetermined amount of a magnitude of the supply voltage signal.

Abstract: A method of concealing bit errors in a signal is provided. The method comprises encoding a signal parameter according to a set of constraints placed on a signal parameter quantizer. The encoded signal parameter is decoded and compared against the set of constraints. Finally, the method includes declaring the decoded signal parameter invalid when the set of constraints is violated.

Abstract: A semiconductor wafer configured for in-process testing of integrated circuitry fabricated thereon. At least two die are separated by a scribe area, and each of the die has at least one complementary metal oxide silicon (CMOS) static random access memory (SRAM) array embedded therein among mixed-signal CMOS circuitry. The mixed-signal CMOS circuitry includes devices with larger feature sizes compared to similar devices of the embedded SRAM array. A first process control monitor (PCM) testline is included, which has a first layout corresponding to the mixed-signal CMOS circuitry. Additionally, a second PCM testline is included, which has a second layout corresponding to the embedded SRAM arrays. The first and second PCM testlines are formed in the scribe area.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A converter. The elements are intended to be of equal value, however, regardless of whether they are or not. A circuit is used to randomly select subsets of elements according to a bi-directional selection technique in order to effectively rending the elements or components of equal value. Associated with each component is a switch, and a subset of the plurality of components are correspondingly switched in successive order progressing in a first direction and, subsequently, in successive order progressing in a second direction opposite the first direction. Connecting components in a first direction from left-to-right follows by selecting components in a second direction from right-to-left, and then again selecting components in the first direction from left-to-right, and so forth.

Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.

Abstract: An integrated VCO having an improved tuning range over process and temperature variations. There is therefore provided in a present embodiment of the invention an integrated VCO. The VCO comprises, a substrate, a VCO tuning control circuit responsive to a VCO state variable that is disposed upon the substrate, and a VCO disposed upon the substrate, having a tuning control voltage input falling within a VCO tuning range for adjusting a VCO frequency output, and having its tuning range adjusted by the tuning control circuit in response to the VCO state variable.

Abstract: A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A transmitting device applies an outer code, which may include, for example, a block code, an exclusive OR (XOR) code, or a repetition code, to one or more packets prior to adaptation of the packets for transmission over the physical (PHY) layer of the communications system, wherein the PHY layer adaptation may include FEC encoding of individual packets. The outer coded packets are then separately transmitted over a channel of the communications system. A receiving device receives the outer coded packets, performs PHY level demodulation and optional FEC decoding of the packets, and then applies outer code decoding to the outer coded packets in order to restore packets that were erased during transmission due to burst noise or other impairments on the channel.

Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: Devices and methods relating to a multi-port register file memory including a plurality of storage elements in columns are disclosed. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12, 14, 16 and corresponding stages of intermediate data 18, 20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude contained in the symbol is detected 28 and compared with a threshold. If the peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12,14,16 and corresponding stages of intermediate data 18,20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude that the symbol would contain after the subsequent processing in the analogue front end 146 is modelled and compared with a threshold. If the modelled peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated. The symbols stored in the buffer are output through the analogue front end 146.

Abstract: A multi-tone modem processes an input data stream 10 and uses an inverse Fourier transform 24 to produce a stream of multi-tone symbols 26 fed to an analogue front end 146. A model 32 models the subsequent processing in the analogue front end 146 and outputs a control signal 184 that controls the analogue front end 146 accordingly.

Abstract: A system for detecting collisions in a shared communications medium, such as a TDMA medium, includes a receive path adapted to generate a first intermediate signal, a second intermediate signal, and a data symbol sequence from an input signal. A preamble detection module generates a correlation metric from the first intermediate signal. A power measurement module generates a power indication signal from the second intermediate signal. A noise measurement module generates a noise indication signal from the second intermediate signal and the data symbol sequence. A processing module is adapted to characterize the input signal as a collision for certain values of correlation metric, power indication signal, and noise indication signal.

Abstract: A charge pump includes at least one switching transistor for switching current on or off in response to an up or down signal, a pair of transistors (one coupled to the source and the other to the drain of the switching transistor) each having its source and drain shorted and coupled to receive a complement of the signal on the gate terminal of the switching transistor on their gate terminals, and a fourth transistor coupled to the drain of the switching transistor and a power supply. The pair of transistors are activated concurrent with the deactivation of the switching transistor. The fourth transistor may provide for active shutoff of a current transistor being switched by the switching transistor, by actively charging the source of the current transistor to a voltage which is not exceeded by the gate terminal of the current transistor.