Abstract: Disclosed are various embodiments of a network switch for storing a prefix address and a mask corresponding to the prefix address, the prefix address and the mask each representing a binary value, the mask representing a number of significant bits of an address beginning with a most significant bit. The network switch obtains a network frame via one of a plurality of network interfaces, the network frame comprising a network address in a header of the network frame, the network address being a binary value representing a physical address of a network interface device. The network switch determines a truth value associated with a comparison of a mask number of bits of the prefix and network addresses, the truth value indicating an equivalence of the comparison. In response to the truth value, the network switch may initiate at least one action associated with the network frame.

Abstract: An auxiliary reduced power analog-to-digital converter (ADC) is provided for use during sleep periods of a receiver. The auxiliary ADC has a reduced dynamic range but sufficient accuracy to allow demodulation of signaling information contained in an input signal and to update control parameters used for synchronization and channel estimation. As such, a main higher power, higher dynamic range ADC can be turned off during sleep periods, reducing receiver power consumption. The main ADC is turned on at the end of a sleep period, and the receiver can be ready for receiving data immediately using the main ADC because the control parameters are maintained up to date during the sleep period using the auxiliary ADC.

Abstract: A communication device having a Media Access Control (MAC) layer and a physical (PHY) layer may include a first physical channel for transferring at least one packet between the PHY layer and the MAC layer. The communication device may further include a second physical channel for transferring, to a transmitting device, a first table that indicates a number of bits to be loaded onto each of a plurality of tones and a second table that indicates a transmission power for the plurality of tones. The PHY layer may receive the at least one packet from the transmitting device over the plurality of tones and may transfer the at least one packet to the MAC layer via the first physical channel.

Abstract: A radio circuit includes a front-end module, a board, a liquid MEMS component, and a coupling component. The front-end module is implemented on at least one integrated circuit (IC) die and includes a variable circuit. The variable circuit is adjustable to facilitate an operational adjustment of the front-end module for a given operational condition of the radio circuit. The board supports the liquid MEMS component and supports, at least indirectly, the at least one IC. The coupling component electrical couples the liquid MEMS component to the variable circuit, wherein, based on a control signal, one or more characteristics of the liquid MEMS component is changed, which adjusts the variable circuit.

Abstract: An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library.

Abstract: A system and method for frequency division multiplexed high speed physical layer devices. A next generation Ethernet device can be generated through reuse of existing architectures. Multiple instantiations of an existing architecture can be supported on a given wire pair by frequency division multiplexing on a number of carriers. The multiple instantiations can enable multiple modes that can support different configurations, variable rates, and energy efficient Ethernet.

Abstract: Embodiments of the present invention are directed to a wireless-enabled component (WEC) for enabling a wireless bus for intra-chip and inter-chip communication. A WEC encompasses a functional block of an IC (such as, for example, a processing core of a processing unit), an entire IC (such as, for example, a processing unit), or a device that includes a plurality of ICs (such as, for example, a handheld device). According to embodiments, a WEC may be associated with one or more sub-blocks of an IC, a single IC, or a plurality of ICs.

Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding, reference source without any substantial affect upon its full scale output.

Abstract: A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a frequency divider that is configured to apply a correction voltage to a feedback of the output frequency signal, the correction voltage being a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal.

Abstract: A touch sensitive pad with a plurality of touch sensitive elements and processing circuitry coupled to a communications interface and to the touch sensitive pad for scanning the plurality of touch sensitive elements to measure a plurality of touch sensitive element values. The plurality of touch sensitive element values is compared to a hovering finger threshold pattern. Upon a favorable comparison, a hovering finger condition is determined, and a position of the hovering finger in three-dimensions is detected with respect to the touch sensitive pad. The plurality of touch sensitive element values is compared to a touching finger threshold pattern. Upon a favorable comparison, a touching finger condition is determined, and a position of the touching finger is detected upon the touch sensitive pad.

Abstract: A method and apparatus for transmit signal pulse shaping. Automotive vehicle manufacturers that incorporate electronic components into an automotive vehicle must consider emission requirements masks that can be dependent on particular geographic markets as well as the other electronic components contained within a particular automotive vehicle design. A physical layer device is provided that can be configured to operate in multiple emissions configurations using configurable parameters.

Abstract: A system and method for switching in an energy efficient network. Rapid switching between multiple operating modes can generate a voltage spike or voltage lag on an on-board inductor. Suppression of the voltage spike or voltage lag can be enabled through the activation of by a physical layer device of an inductor bypass path at a time proximate to the switching between multiple operating modes.

Abstract: A framework for enabling a user equipment (UE) to apply interference suppression processing during network conditions that are favorable to interference suppression or that are known is provided. The framework includes an interference suppression (IS) time and frequency (time/frequency) zone, which can be scheduled by a serving base station and signaled to the UE. In an embodiment, the serving base station coordinates with the interfering base station(s) to create a network condition favorable to interference suppression at the UE during the IS time/frequency zone. In another embodiment, the serving base station opportunistically schedules the IS time/frequency zone for the UE whenever it determines favorable transmission parameters being used or scheduled for use by the interfering base station(s). The UE applies interference suppression processing within the IS time/frequency zone, thereby improving receiver performance.

Abstract: Power distribution circuitry to improve wireless power distribution and facilitate wireless power transfer (WPT) operations in a wireless communication device under a variety of operating conditions. In various exemplary embodiments of the disclosure, the power distribution circuitry operates to provide a wireless power (WP) supply voltage to wireless communication circuitry of the device in order enable a WPT connection procedure under certain low power conditions. Such conditions might include a power off mode, a sleep mode, and dead/low battery operating conditions wherein the available battery supply voltage is less than a threshold voltage required to enable device components. The power distribution circuitry may switch the supply voltage of the wireless communication circuitry to another available supply voltage source after the WPT connection procedure is completed and wireless power is being received by the wireless communication device.

Abstract: A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Abstract: A system for hierarchical hashing for longest prefix matching may include a memory and a processor. The memory may be configured to store hash tables that include prefixes and associated next hop information, where the hash tables are associated with lengths of the prefixes and at least one of the hash tables is associated with a range of lengths of the prefixes. The processor may be configured to determine a destination address associated with a packet received over a first port, determine next hop information associated with a longest prefix that matches the destination address by searching at least a first hash table of the hash tables that stores a largest number of the prefixes relative to the hash tables, and prepare the packet for transmission over a second port that is determined based at least on the next hop information.

Abstract: A wireless communication device includes a communication interface and a processor that operate to generate a first transmission stream by processing first information based on first parameter(s) and a second transmission stream by processing second information based on second parameter(s). In some examples, the second at least one parameter is relatively less robust than the first at least one parameter, and the second information augments the first information when combined with the first information. The wireless communication device then transmits the first transmission stream and the second transmission stream to at least one other wireless communication device. Examples of such parameters include forward error correction (FEC) code, error correction code (ECC), modulation coding set (MCS), modulation type including a mapping of constellation points arranged in a constellation, power (e.g.

Abstract: A device with concurrent long-term evolution (LTE) and WLAN uplink transmission includes a WLAN transceiver coupled to an LTE transceiver via an interface. The LTE transceiver includes an LTE Layer-1 module that determines whether an LTE data downlink activity is scheduled for an LTE downlink sub-frame of an LTE time frame, based on information in a first portion of the LTE downlink sub-frame. When determination is made that the LTE data downlink activity is not scheduled for the LTE downlink sub-frame, a message may be communicated through the interface to notify the WLAN transceiver that the second portion of the LTE downlink sub-frame is available for WLAN communication. The LTE time frame includes multiple LTE downlink sub-frames each including the first portion and a second portion. The first portion provides the information that indicates whether the LTE data downlink activity is scheduled for the second portion of that LTE sub-frame.

Abstract: A method of transferring data in a network is provided. Data is received at a sub-switch of a first bundled switch having a plurality of sub-switches, the sub-switch being configured to only couple to connections external to the first bundled switch. The method also includes transferring the data from the first bundled switch using a multi-lane cable coupled to a second bundled switch, a first end of the multi-lane cable coupled to a sub-switch in the first bundled switch and a second end of the multi-lane cable coupled to at least two sub-switches in the second bundled switch.

Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.