Abstract: A receiver includes an antenna array that generates a plurality of received signals from at least a first remote transmitter and a second remote transmitter, the antenna array having a beam pattern that is controllable based on at least one control signal. A plurality of receiver sections process the plurality of received signals to generate a plurality of down-converted signals.

Abstract: A method and apparatus of the present invention support operation of a device, such as a WLAN device in a plurality of frequency bands. The WLAN selects a frequency band of operation by determining a quality indicator. The quality indicator for the selected frequency range considers a channel power and interference power for the selected frequency range. The WLAN further selects a communication protocol. The inventive WLAN devices includes a first baseband processor interface, a first radio for receiving the digital data and for transmitting RF signals, a second baseband processor interface and a second radio for receiving the digital data and for transmitting RF signals in a first frequency band and for receiving RF signals in the first frequency band and for producing corresponding digital data to the second baseband processor interface.

Abstract: Aspects of a method and system for identifying a radio frequency identification (RFID) tag location using a switchable coil are presented. Aspects of the systems may include one or more processors that enable selection of an inductor coil from a plurality of inductor coils. The selection of the inductor coil may be based on a change in an electromagnetic field, with respect to an initial electromagnetic field, as detected by the selected inductor coil. The processors may enable transmission of a signal, having a transmitter frequency in the UHF frequency band, via the selected inductor coil.

Abstract: Digital to analog converter (DAC) with ternary or tri-state current source. A DAC including a number of ternary or tri-state devices operates based upon codewords provided thereto. Generally, each respective codeword bit directs operation of one of the respective ternary or tri-state devices within the DAC. Each ternary or tri-state device operates in at least three respective operational states (e.g., based upon the respective values of +1, ?1, or 0 being provided thereto). In a current source implementation, each respective current source is implemented to deliver current, draw current, or neither delivered or draw current. In a voltage source implementation, each respective voltage source is implemented to provide a positive voltage, a negative voltage, or provide no voltage. A DAC coding table may be designed based upon characterization of codewords provided to one or more DACs (e.g., based upon a distribution, a probability density function (PDF), etc. of such codewords).

Abstract: Rollover operative digital to analog converter (DAC). With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to compare the codeword to threshold(s) in accordance with adaptively partitioning the codeword into one or more sub-codewords when the codeword has a magnitude greater than at least one of the thresholds. In instances that the codeword is less than a threshold, the codeword may be provided directly to a DAC for use in generating a first analog signal. However, if the codeword is a larger than a threshold, then that portion of the codeword which is greater than the threshold may be provided to an alternative component such as one or more auxiliary or additional DACs, one or more other circuitry components, etc. in accordance with generating at least one additional analog signal to be combined with the first analog signal.

Abstract: The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse.

Abstract: Dual digital to analog converters (DACs) with codeword parsing. With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to divide, partition, etc. the codeword into different respective sub-codewords as may be provided to two or more DAC's. Adaptation with respect to differently generated sub-codewords with respect to different respective codewords may be made in terms of any one or more of a variety of characteristics, including sub-codeword width (e.g., the number of bits included within a sub-codeword), quantization steps, etc. Moreover, such adaptation may be in consideration of any one or more local and/or remote operating characteristics of one or more devices, communication links, etc. within a communication system or network. Different respective sub-codewords undergo processing by different respective DAC's in generating respective analog signals for combination in generating a final or output analog signal.

Abstract: Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion.

Abstract: Techniques are described herein that use sensors (e.g., microphones) for noise reduction in a mobile communication device. For example, one technique enables a first sensor that is initially configured to be a speech sensor to be used as a noise reference sensor. This technique also enables a second sensor that is initially configured to be a noise reference sensor to be used as a speech sensor. Another technique enables a primary sensor and/or a secondary sensor in a handset of a mobile communication device to be used as a speech sensor while a sensor in a headset of the mobile communication device is used as a noise reference sensor, or vice versa. In yet another technique, a secondary sensor in a mobile communication device is configured to be a directional sensor.

Abstract: Techniques are described herein that suppress noise using multiple sensors (e.g., microphones) of a communication device. Noise modeling (e.g., estimation of noise basis vectors and noise weighting vectors) is performed with respect to a noise signal during operation of a communication device to provide a noise model. The noise model includes noise basis vectors and noise coefficients that represent noise provided by audio sources other than a user of the communication device. Speech modeling (e.g., estimation of speech basis vectors and speech weighting) is performed to provide a speech model. The speech model includes speech basis vectors and speech coefficients that represent speech of the user. A noisy speech signal is processed using the noise basis vectors, the noise coefficients, the speech basis vectors, and the speech coefficients to provide a clean speech signal.

Abstract: A dynamically programmable security device. The device includes: a secure nonvolatile read only memory (NVMROM) for securely storing a unique device cipher key; a secure interface for dynamically loading authenticated application code; a cryptographic engine for encrypting, decrypting data and authenticating the application code; a secure random access memory (RAM) for storing the authenticated application code and application data; and a processor for executing the authenticated application code.

Abstract: A firmware data processing system may be operable to allocate a configuration area in the firmware binary image file for customizable settings. During the firmware build process for the firmware binary image file, default configuration information may be inserted into this configuration area. This default configuration information may be either actual default setting values or indicator to use the default setting values. During post-build modification process, a separately created utility application may be operable to read in the original firmware binary image file, select new settings, and insert new configuration information into the configuration area. The utility application may also be operable to create a new firmware binary image file with reproduced checksums or other error detection mechanisms required for the original firmware binary image file, based on the new configuration information in the configuration area.

Abstract: Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion.

Abstract: Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

Abstract: Embodiments of the present invention are directed to providing an increased trace width when traversing a void in another layer in a printed circuit board or package design. By increasing the trace width or alternatively increasing the capacitance, the degradation due to the void can be reduced. This approach works for microstrip, stripline as well as other transmission lines that use a reference plane. The void can be the result of an antipad associated with a via, or any other disruption in an otherwise uniform reference plane.

Abstract: A Voice-Data-RF IC includes a baseband processing module, an RF section, and an interface module. The baseband processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. The RF section converts an inbound RF voice signal into the inbound voice symbol stream, converts the outbound voice symbol stream into an outbound RF voice signal, converts an inbound RF data signal into the inbound data symbol stream, and converts the outbound data symbol stream into an outbound RF data signal. The interface module provides coupling between the baseband processing module, the RF section, and with off-chip circuits.

Abstract: Techniques are described herein that synchronize media streams using time signal(s) from an independent time source. An independent time source is a time source that is independent from (i.e., that is not connected to) an asynchronous data network via which the media streams are transferred. In accordance with the techniques described herein, media server(s) transfer the media streams to client(s) via an asynchronous data network. The independent time source provides the time signal(s) to the media server(s) and/or the client(s). If the time signal(s) are provided to the media server(s), the media server(s) may provide timing information that is based on the timing signal(s) to the client(s). The client(s) use the timing information from the media server(s) and/or the timing signal(s) from the timing source to synchronize the media streams.

Abstract: A universal authentication token is configured to securely acquire security credentials from other authentication tokens and/or devices. In this manner, a single universal authentication token can store the authentication credentials required to access a variety of resources, services and applications for a user. The universal authentication token includes a user interface, memory for storing a plurality of authentication records for a user, and a secure processor. The secure processor provides the required cryptographic operations to encrypt, decrypt, and/or authenticate data that is sent or received by universal token. For example, secure processor may be used to generate authentication data from seed information stored in memory.

Abstract: Methods and systems for supplying power to multiple voltage islands using a single supply source are disclosed. Aspects of one method may include providing power to a first of a plurality of voltage islands, and individually controlling providing of power to each of a remaining portion of the plurality of voltage islands. For example, when an electronic system is first powered on, a low current voltage source may be used to supply power to a primary voltage island. As a higher current voltage source becomes available, power derived from the higher current voltage source may be provided to the primary voltage island and to secondary voltage islands. Power to each of the secondary voltage islands may be, for example, individually controlled via a power MOS transistor. The power MOS transistor may also be configured to allow a faster blocking time than unblocking time.

Abstract: Distortion and aliasing reduction for digital to analog conversion. Synthesis of one or more distortion terms made based on a digital signal (e.g., one or more digital codewords) is performed in accordance with digital to analog conversion. The one or more distortion terms may correspond to aliased higher-order harmonics, distortion, nonlinearities, clipping, etc. Such distortion terms may be known a priori, such as based upon particular characteristics of a given device, operational history, etc. Alternatively, such distortion terms may be determined based upon operation of a device and/or based upon an analog signal generated from the analog to conversion process. For example, frequency selective measurements made based on an analog signal generated from the digital to analog conversion may be used for determination of and/or adaptation of the one or more distortion terms. One or more DACs may be employed within various architectures operative to perform digital to analog conversion.