Abstract: A capacitor sharing surge protection circuit for protecting multiple ports from harmful energy surges, such as electrostatic discharge (ESD) and cable discharge events (CDE), is provided. The protection circuit includes a plurality of diodes with respective cathodes and anodes. Each anode of the plurality of diodes is coupled to one of the plurality of ports. A bypass capacitor is coupled between the cathodes of the plurality of diodes and ground. In an embodiment, a bulk capacitor is further coupled between the cathodes of the plurality of diodes and ground.

Abstract: A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device.

Abstract: A network switch that has a plurality of input ports that receive data packets. An external interface is connected to the plurality of input ports. The external interface externally transmits the data packets for processing, and receives the data packets after processing. A memory management unit is connected to the external interface and a plurality of output ports are connected to the memory management unit.

Abstract: A system includes a mobile device providing a plurality of applications and an agent providing first and second authentication procedures for authenticating a user of the mobile device to first and second applications running on the mobile device. A first application is enabled by authenticating a user through a first authentication procedure, and a second application is enabled by authenticating a user through a second authentication procedure. The agent authenticates the user to the first application following the first authentication procedure, and the agent authenticates the user to the second application following the second authentication procedure.

Abstract: A system and method for enabling secure short-range communication. A close proximity transmitter is used that is designed with a relatively poor radiator as compared to a conventional transmitter supporting conventional transmissions such as mobile phone communications, Wi-Fi, or Bluetooth communication. The close-proximity transmitter and the conventional transmitter are selectively activated based on a communication mode.

Abstract: A method for communication is disclosed and may include storing media and meta-data associated with the stored media. The storing may occur at a first location associated with a first communication device. A channel guide including representations of the stored media may be presented, based on the meta-data associated with the stored media, on a television in a second location. The presenting may occur when the first communication device is communicatively coupled to a second communication device at the second location. In response to receiving a selection via the presented channel guide, at least one media file corresponding to the received selection may be displayed based on the meta-data associated with stored media, on the television and/or a media player in the second location. The first communication device may be a media processing unit.

Abstract: A power over Ethernet (PoE) power sourcing equipment (PSE) architecture for variable maximum power delivery. PoE PSE subsystems rely on some control to “turn on” a power field effect transistor (FET), which allows current to be transmitted to a powered device (PD). A hybrid approach is provided where an internal FET can be augmented with an external FET to provide an architecture that can be flexibly applied to applications with various space, cost and cooling limitations. The maximum delivered power can also be boosted with the addition of an external FET to the internal FET.

Abstract: An audio processing system which allows a surround sound system to utilize the transmission bandwidth efficiently by adaptively transmitting a supplementary data from a secondary source in addition to the audio signals of a primary source. The system consists of a transmitter component, capable of transmitting audio signals from a primary source and adaptively inserts supplementary data of the secondary source in the reserved communication bandwidth. The transmitter inserts headers in the channels used by the supplementary data to allow the receivers to identify the channel allocation between the primary source and the secondary source. Another part of the audio processing system is that of a receiver component which is capable of discriminating between data from the primary source and data from the secondary source.

Abstract: A system and method is provided for handling data in wireless communication devices where data may be captured and linked to a personal journal via indexing and mapping of context data tags abstracted from captured data. The captured data may be retrieved by matching a query to one or more context data tags indexed and mapped to the personal journal. A user preference utilizing one or more of the context data tags linked to the personal journal may facilitate captured data retrieval. The captured data may include multimedia data of an event pre-tagged with indexed information such as user ID, time, date, location and environmental condition or optionally one or more user's biometric data in response to the event. The pre-tagged captured data may be stored in the local host device or transferred to a remote host or storage for later retrieval or post processing.

Abstract: A Powered Device (PD) in a Power Over Ethernet system that supports increased cable lengths of more than 100 m is provided herein. The proposed PD design requires no modifications at the PSE side. Embodiments include example modifications of IEEE 802.3af PD system rules, including example modifications of PD classification and port voltage ranges to enable increased cable length PoE.

Abstract: A method and system is provided processing channel information may include in a mobile FM radio system including an integrated FM radio transmitter and FM radio receiver, dynamically generating a list of local FM channels, ranking local FM channels in the generated list, and selecting one of the ranked local FM channels for use by the FM transmitter based on neighboring channel interference. The FM radio receiver may detect FM channels being transmitted or not being transmitted, detect a pilot signal or a channel transmission pause. A tuning frequency of the FM radio receiver may be adjusted for scanning and detecting the local FM channels based on knowledge of a location of the FM radio receiver, received signal strength indicator (RSSI), dynamically scanning for local FM channel based on received RDS/RDBS data or country code, and/or carrier error of a related FM signal.

Abstract: A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.

Abstract: Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.

Abstract: A method and apparatus for communicating between devices is described. In one embodiment, the method comprises one or more communication devices coordinating transmissions of data packets to function as an access point with respect to a first mobile station and a second station wirelessly communicatively coupled to the one or more communication devices, and the one or more communication devices wirelessly transmitting a first packet and a second packet to the first mobile station and the second mobile station respectively at different time or at time when the transmissions overlap, at least partially, based on whether transmissions of the first and second packets would interfere with each other.

Abstract: A system for processing signals is disclosed and may include a single integrated circuit chip. The single integrated circuit chip (SICC) may include one or more processors coupled to a first satellite receiver demodulator and a second satellite receiver demodulator. The SICC may also include one or more video decoders coupled to the one or more processors, and one or more video and graphics display engines coupled to the one or more video decoders. The SICC may further include one or more video encoders coupled to the one or more video and graphics display engines. One or more video digital-to-analog converters and one or more RF modulators may be integrated within the SICC, and the one or more video digital-to-analog converters and the one or more RF modulators may be coupled to the one or more video encoders. The video decoder may include a standard definition MPEG-2 video decoder.

Abstract: A system and method for power sourcing equipment (PSE) detection of a powered device (PD) power failure for power backup. A PSE can power a PD at a low level of power as a backup power source. Upon a failure in the PDs primary power source, the PSE can detect a transient (e.g., current and/or voltage) on the PD load as a signal that the PD requires additional power. The PSE can then allocate increased power to the port by entering into an active state as compared to a backup state. As the PSE is responsive to the detection of the transient, the PSE need not rely on a real-time communication from the PD.

Abstract: A programmable transmitter generates a frame preamble to train a receiver with respect to a communication link format that corresponds to a transmission mode wherein the transmission mode may comprise transmitting the communication link over one or more antennas. Generally, the invention includes generating a preamble with an arrangement that depends upon whether a Greenfield (high data rate) or mixed mode transmission is to occur and that depends upon a number of spatial streams that are to be generated. One format for high data rate transmission includes a short training sequence, a long training sequence and a signal field. The mixed mode transmission further includes a legacy prefix.

Abstract: A dual band high isolation antenna structure includes a diplexer unit, a 4-port decoupling module, a first frequency band antenna assembly, and a second frequency band antenna assembly. The diplexer unit is operable to frequency domain multiplex between a first frequency band and a second frequency band. The 4-port decoupling module is operably coupled to the diplexer unit and is operable to isolate a first pair of ports from a second pair of ports. The first frequency band antenna assembly is operably coupled to the diplexer unit and is operable to transceive wireless signals in the first frequency band. The second frequency band antenna assembly is operably coupled to a port in each of the first and second pairs of ports and is operable to transceive wireless signals in the second frequency band.

Abstract: Imbalance and distortion cancellation for composite analog to digital converter (ADC). Such an ‘ADC’ is implemented using two or more ADCs may be employed for sampling (e.g., quantizing, digitizing, etc.) of an analog (e.g., continuous time) signal in accordance with generating a digital (e.g., discrete time) signal. Using at least two ADCs allows for the accommodation and sampling of various signals having a much broader dynamic range without suffering degradation in signal to noise ratio (SNR). Generally, the signal provided via at least one of the paths corresponding to at least one of the respective ADCs is scaled (e.g., attenuated), so that the various ADCs effectively sample signals of different magnitudes. The ADCs may respectively correspond to different magnitude and/or power levels (e.g., high power, lower power, any intermediary power level, etc.). Various implementations of compensation may be performed along the various paths corresponding to the respective ADCs.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit includes a WLAN interface, an input buffer, an input buffer controller, and a processor. The WLAN transceiving integrated circuit may also include an output buffer, an output buffer controller, a transcoder, and/or an audio Coder-Decoder (CODEC). The WLAN transceiving integrated circuit is installed in a WLAN device that services voice communications. The input buffer receives packetized audio data from the WLAN interface. When the input buffer satisfies a buffer vacancy threshold, the processor and the input buffer controller cooperatively operate to fill at least a portion of the input buffer with packetized audio data. The processor copies packetized audio data from the input buffer and fills the input buffer with the copied packetized audio data to maintain an audio pattern in the input buffer. The input buffer controller fills the input buffer when the processor is available and after copying/filling is no longer effective.