Abstract: Methods and systems for digitally controlling transmitter gain compensation are disclosed. Aspects of one method may include applying an effective negative resistance to differential outputs of amplifying circuitry to compensate for gain changes that may be due to temperature changes. The effective negative resistance may be provided via a plurality of load circuits coupled in parallel to the differential outputs. The plurality of load circuits may have similar effective negative resistances, or the plurality of load circuits may be binary weighted. Each load circuit may be selected via digital control signals that may enable the load circuit. This may allow adjusting of the effective negative resistance by selecting different load circuits.

Abstract: A radio frequency integrated circuit (RFIC) includes a digital to analog converter, an analog to digital converter, and a low noise amplifier. The digital to analog converter (DAC) is operably coupled to convert outbound symbols into outbound baseband signals, wherein the digital to analog converter is fabricated within a DAC portion of a substrate of the RFIC. The analog to digital converter (ADC) is operably coupled to convert inbound baseband signals into inbound symbols, wherein the analog to digital converter is fabricated within an ADC portion of the substrate. The low noise amplifier is operably coupled to amplify an inbound radio frequency (RF) signals. The low noise amplifier is fabricated within a radio portion of the substrate, wherein the DAC portion of the substrate is physically between the ADC portion and the radio portion of the substrate to provide isolation when the low noise amplifier and the ADC are active and the DAC is inactive.

Abstract: Bursts of data are managed. Data is stored in a machine readable memory device a first time at a first memory address. The machine readable memory device has one or more burst boundaries. The first memory address has a first alignment with respect to the burst boundaries. The data is stored in the machine readable memory device a second time at a second memory address. The second memory address has a second alignment with respect to the burst boundaries.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status registers containing interrupt status information for the plurality of channels, interrupt sources are specifically assigned to individual processors in the multiprocessor device so that the assigned processor can efficiently determine the source and priority of an interrupt by reading the register information.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes at least one processing device, an IR processing function, and IR memory. The at least one processing device is operable to receive analog signals corresponding to a data block, to sample the analog signals to produce samples, to equalize the samples to produce soft decision bits corresponding to the data block, and to initiate IR operations. The IR processing function is operable to perform IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block. The IR memory operably couples to the IR processing function, includes Type I IR memory adapted to store IR status information of the data block, and includes Type II IR memory adapted to store the data block.

Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices.

Abstract: Certain embodiments of the invention may be found in a method and system for single sideband mixing receiver architecture for improving signal quality in an RF communication system. An embodiment of the invention may mix a first input signal with a first local oscillator signal, via a first mixer, to generate a first mixed output signal. It may also mix a second input signal with a second local oscillator signal, via a second mixer, to generate a second mixed output signal. It may then generate a single sideband signal by adding the first mixed output signal and the second mixed output signal. The removal of one of two sidebands may reduce noise at the desired signal, since the removed sideband may have been at the same frequency as the desired signal.

Abstract: Certain embodiments for debugging mechanism for flow control based designs may comprise a debugging interface module between a transmitter and a receiver, all integrated on a chip. At least one debugging entity, which may be on the chip or off the chip, may indicate to the debugging interface module to initiate debug mode via command signals. In debug mode, the control signals between the transmitter and the receiver may be intercepted by the debugging interface module to halt normal data flow from the transmitter to the receiver. The debugging entity may then transmit data to the receiver, while the transmitter is disabled, or receive data transmitted by the transmitter, while the receiver is disabled. When the debugging entity indicates to the debugging interface module to end debug mode, normal data flow may continue, and the debugging interface module may appear transparent to the data flow.

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: Carrier detection applicable for SISO, MIMO, MISO, and SIMO communications. A novel approach is presented to perform carrier detection for a signal found in any of a wide variety of communication systems including single-input-multiple-output (SISO), multiple-input-multiple-output (MIMO), multiple-input-single-output (MISO) single-input-multiple-output (SISO), communication systems. This novel approach to performing carrier detection is more robust than those approaches existent in the art. By employing normalization with respect to power in determining a modified correlation function, there is less susceptibility to false detects. Also, this approach is quite robust to any circuitry DC offsets that may undesirably exist within a communication device that undergoes operational changes due to a variety of factors including environmental perturbations and/or changes in processing circuitry within the communication device (e.g., changes in gain control).

Abstract: An analog front end. The analog front end comprises a converter configured to convert a differential input signal to a single-ended input signal, and convert a single-ended output signal to a differential output signal. And a transformer configured to couple the differential input signal from a twisted pair telephone line to the converter, and couple the differential output signal from the converter to the twisted pair telephone line.

Abstract: A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time Bluetooth functionality for an upper limit of Bluetooth slave devices. The microsequencer includes a 72-bit correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with a 72-bit arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating Bluetooth timing functionality, and at least four registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data.

Abstract: A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.

Abstract: There is disclosed a receiver for receiving a multi-band DMT signal. The receiver includes a plurality of demodulators, each demodulator having a discrete Fourier transform and being provided to demodulate a respective one of a plurality of bands in the multi-band signal, the multi-band signal being modulated in an inverse discrete Fourier transform. A method of demodulating a multi-band signal is also provided.

Abstract: A method and apparatus for dynamic frequency selection in a wireless communication system or network includes processing that begins when an access point determines interference on a wireless channel that is being used by the access point. When the interference exceeds an interference threshold, the access point provides a request packet to affiliated stations being serviced by the access point for channel spectrum information. The processing continues as the affiliated stations generate the channel spectrum information regarding each of the wireless channels in the wireless communication network. The processing proceeds then as the affiliated stations provide the channel spectrum information to the access point via the current wireless channel. The access point interprets the channel spectrum information to determine a desired wireless channel of the plurality of wireless channels within the wireless communication network.

Abstract: Described herein are systems and methods for determining data rate in a direct sequence spread spectrum system. The systems may include circuits or processors for receiving a signal that was transmitted at an unknown data rate and determining the value of the unknown data rate based on a sequence of bits that is generated from processing the signal according to a first data rate. The methods may include receiving a signal having an unknown data rate, processing the signal according to a first data rate, generating another signal that corresponds to a sequence of bits that result from the processing, and determining the value of the unknown data rate according to the sequence of bits.

Abstract: A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.

Abstract: Rate control adaptable communications. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single decoder is operable to decode each of the various rates at which the data is encoded by the encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on a variety of operational parameters including operating conditions of the communication system, a change in signal to noise ratio (SNR), etc.