Abstract: A system and method for meeting performance goals in an electronic system in an energy efficient manner. Various aspects of the present invention may comprise operating an electrical circuit at a current level of performance and a current level of energy efficiency by providing the electrical circuit with electrical power characterized by a current set of power characteristics (e.g., utilizing a power control module). The current level of performance may be determined (e.g., by a performance monitor) and compared to a desired level of performance (e.g., by the power control module). If the current level of performance is higher than the desired level of performance, then the electrical circuit may be operated at a next (e.g., lower) level of performance and a next (e.g., higher) level of energy efficiency by providing the electrical circuit with electrical power characterized by a next set of power characteristics.

Abstract: High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and a particular phase within that sector. Generally, this range from 0° to 360° is uniformly divided so that each sector is the same. However, if desired, there can alternatively be differences in the sizes of each of the sectors. The use of these two sets of controls signals (one for selecting the sector and one for selecting the particular phase within the sector) allows for very few control signals. N-channel metal oxide semiconductor field-effect transistor (N-MOSFET) based switches and differential pairs of transistors or alternatively p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) based switches and differential pairs of transistors can be employed.

Abstract: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the switches of the array, and an output signal is taken from the nodes at ends of the resistor. The high voltage level of such an output driver is truly the level of the power supply energizing the circuit (e.g., VDD) while still consuming relatively low power.

Abstract: A system and method for using an Ethernet physical layer device to identify cabling topologies. A power sourcing equipment (PSE) can power independent powered devices (PDs) using two sets of wire pairs in a single four-pair cable. Higher power PSEs can power a single PD using all four wire pairs in the cable. Conventional power over Ethernet (PoE) analog techniques (i.e., voltage, current, etc.) have a difficult time distinguishing where the wire pairs are going from the PSE. By using information (e.g., negotiated speed, link energy, distance diagnostic, etc.) generated by the physical layer device (PHY) subsystem, the PoE system can determine whether the two sets of wire pairs in a cable are powering a single PD or two independent PDs.

Abstract: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

Abstract: A technique is described herein for reducing audible artifacts in an audio output signal generated by decoding a received frame in a series of frames representing an encoded audio signal in a predictive coding system. In accordance with the technique, it is determined if the received frame is one of a predefined number of received frames that follow a lost frame in the series of the frames. Responsive to determining that the received frame is one of the predefined number of received frames, at least one parameter or signal associated with the decoding of the received frame is altered from a state associated with normal decoding. The received frame is then decoded in accordance with the at least one parameter or signal to generate a decoded audio signal. The audio output signal is then generated based on the decoded audio signal.

Abstract: A capacitive structure formed in an Integrated Circuit (IC) includes a plurality of capacitor node conductor pairs, each including a first node conductor having a base portion and a plurality of finger portions and a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor. Dielectric is horizontally disposed between the first node conductor and the second node conductor. At least one dielectric layer vertically separates adjacent metal layers, each dielectric layer including dielectric disposed between the adjacent metal layers, a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers, and a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers.

Abstract: Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes a thick film material that forms a opening, a die, an insulating material, a redistribution interconnect on the insulating material, and a ball interconnect. The die is positioned in the opening. The insulating material covers the die and a surface of the thick film material, and fills a space adjacent to the die in the opening. The redistribution interconnect is formed on the insulating material. The redistribution interconnect has a first portion coupled to a terminal of the die through the layer of the insulating material, and a second portion that extends away from the first portion over the insulating material filling the space adjacent to the die in the opening. The ball interconnect is coupled to the second portion of the redistribution interconnect.

Abstract: A method and apparatus for providing improved security and improved roaming transition times in wireless networks. The same pairwise master key (PMK) from an authentication server can be used across multiple access points and a new pairwise transition key (PTK) is derived for each association of a station to any of the access points. A plurality of access points are organized in functional hierarchical levels and are operable to advertise an indicator of the PMK cache depth supported by a group of access points (N) and an ordered list of the identifiers for the derivation path. Access points in each level in the cache hierarchy compute the derived pairwise master keys (DPMKs) for devices in the next lower level in the hierarchy and then deliver the DPMKs to those devices. An access point calculates the PTK as part of the security exchange process when the station wishes to associate to the access point. The station also computes the PTK as part of the security exchange process.

Abstract: A system and method for power sourcing equipment (PSE) detection of a powered device (PD) power failure for power backup. A PSE can power a PD at a low level of power as a backup power source. Upon a failure in the PDs primary power source, the PSE can detect a transient (e.g., current and/or voltage) on the PD load as a signal that the PD requires additional power. The PSE can then allocate increased power to the port by entering into an active state as compared to a backup state. As the PSE is responsive to the detection of the transient, the PSE need not rely on a real-time communication from the PD.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: An apparatus is disclosed that includes first transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a first Ethernet communication protocol at a first data rate, second transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a second Ethernet communication protocol at a second data rate; and third transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a third Ethernet communication protocol at a third data rate.

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract: Methods, devices and systems for wireless communication generate signals by determining whether legacy devices are within a proximal region of the wireless communication. When at least one legacy device is within the proximal region, a frame is formatted to include a preamble field, a signal field, and a data field. Further, the uncoded bits are encoded according to a coding format. The coding format is determined according to bits in the preamble and applicable sub-field lengths.

Abstract: A multimode communication device with a shared signal path programmable filter and a method for utilizing a shared signal path programmable filter in a multimode communication device. Various aspects of the present invention comprise a first module adapted to receive a first communication signal (e.g., corresponding to a first communication protocol) and a second module adapted to receive a second communication signal (e.g., corresponding to a second communication protocol). A shared filter, communicatively coupled to the first and second modules, may be adapted to filter the first and/or second communication signals in accordance with a plurality of selectable sets of filter response characteristics (e.g., associated with the first and second communication protocols). A filter control module may be adapted to select a set of filter response characteristics from a plurality of such sets and program the shared filter to filter a communication signal in accordance with the selected set.

Abstract: A method and system are provided for synthesizing a number of corrupted frames output from a decoder including one or more predictive filters. The corrupted frames are representative of one segment of a decoded signal (sq(n)) output from the decoder. The method comprises determining a first preliminary time lag (ppfe1) based upon examining a predetermined number (K) of samples of another segment of the decoded signal and determining a scaling factor (ptfe) associated with the examined number (K) of samples when the first preliminary time lag (ppfe1) is determined. The method also comprises extrapolating one or more replacement frames based upon the first preliminary time lag (ppfe1) and the scaling factor (ptfe).

Abstract: A method and related computer program product for migrating legacy data to a RAID array while contemporaneously providing user access to legacy data, comprising connecting the legacy drive to the RAID controller, converting the legacy drive into a legacy array, selecting the legacy array and selecting the RAID array to migrate the legacy data to.

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

Abstract: A method and associated system for processing a plurality of replicas of a signal in a signal processing chain, the method includes receiving each of the plurality of replicas of the signal at one of a corresponding plurality of respective antenna elements and orthogonally multiplexing the replicas of the signal on to a single processing chain. The multiplexed replicas are down converted from RF to baseband and converted from an analog to a digital multiplexed signal. The digital multiplexed replicas are then demultiplexed into a plurality of separate signals that correspond to replicas of the signal received at respective ones of the plurality of antennas. In variations, the orthogonal multiplexing includes frequency spreading the replicas of the signal on the single processing chain in accordance with complex Walsh codes. In other variations, the signal replicas are offset in phase by 90 degrees and time multiplexed on the single processing chain.

Abstract: A low-noise transmitter architecture and method for high linearity, high output-swing systems such as Asymmetrical Digital Subscriber Line (ADSL) systems. The transmitter uses a switched-current DAC having a current source coupled to ground, followed by a current-to-voltage converter. The resistance of the current source is typically large enough so that noise from an op-amp included in the current-to-voltage converter is not significantly amplified at the output. The current source may be passive and may include at least one resistor connected to ground. With a passive current source, portions of a signal output by the DAC enter either the current source or the current-to-voltage converter, but not both, eliminating noise in the system produced by the current source.