Abstract: A data processing system contains a processor supporting instructions and operands utilizing a Narrow word size. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. The translation between Narrow and Wide word sizes can be either at a byte/Unicode level, or at a word level.

Abstract: Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).

Abstract: In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by loading the safe store buffer from a safe store stack frame, then delaying loading registers either until actually utilized, or by a background process that loads registers utilizing unused memory cycles. A flag is used for each register that indicates whether the register contents are valid. This flag is cleared for each of the registers whenever such a state transition is made. Then, the flag is set for a register when it is referenced and made valid.

Abstract: A slave device, connected directly to a system bus, which system bus requests the execution of a complex communication protocol, is controlled by another device, connected to the system bus, which identifies the slave device as the target of a transaction on the system bus, executes the communication protocol and sends to the slave device through an auxiliary interface a first identification signal, a second signal for instructing execution of the transaction, and receives from the slave device, through the auxiliary interface, a transaction executed signal. In this way the interface logic of the slave device is reduced to the minimum since the slave device is not required to execute the communication protocol.

Abstract: A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe, constituting serially-coupled registers, is used to step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline.

Abstract: Interface bridge (13) between a system bus (ASBUS) and at least one local bus (11, 12), the system space directly addressable through said system bus being greater than the system space directly addressable through the local bus, comprising a plurality of programmable decoders (17, 18, 19) each of which defines a distinct range within the range directly addressable through the local bus, and a range attribute as range of local bus addresses to be translated or to be transferred directly to the system bus and also identifies a local bus address as being included or otherwise within the range, so that depending on whether the local bus address belongs to one of the ranges or not and on the range attribute, the local bus address is transferred to the system bus as a direct address or as an address translated by a translation logic (20, 21) and capable of addressing the entire system space.

Abstract: Dynamic random access memory with variable configuration depending on the number and capacity of standard memory modules, of DIMM type plugged into a first plurality of slots of a memory motherboard comprising a control unit, into which it is possible to plug, into the first plurality of slots, in substitution for the memory modules, expansion supports, in turn provided with a second plurality of slots for the insertion of standard memory modules of DIMM type, and of column address latch registers each associated with a slot of the second plurality and thereby to support and allow the configurability and operability of interleaved-block memory, and access cycles, with partial time overlap, without renouncing the use of commercially available DIMM memory modules and without burdening the basic memory configuration with all the overheads required to support the interleaved-block configuration.

Abstract: A method and system for facilitating the creation of warehouse requests in a data warehouse system. During the design of the data warehouse tables, a repository tool is used for storing a number of new objects such as source and target databases, source and target tables and warehouse requests that are graphically defined and linked together by an administrator with the repository tool. The resulting visual design is so drawn so as to serve as input for each warehouse request to be generated. The administrator invokes a data replication component that operatively couples to the repository tool signaling that the warehouse request is to be implemented. The data replication component automatically creates the different subcomponents of the request by accessing various links stored by the repository tool and displays a visual representation of the subcomponents and their relationships to each other to the administrator.

Abstract: A method and database organization for use by a plurality of client systems wherein a database contains a plurality of table structures for storing a product directory index and a minimum number of product related information entries utilized in generating a bill of materials document for a particular user designated customer product. The system also includes a selection menu facility component and a data selection component, both of which operatively couple to the database. The selection menu facility component enables an operator to access the product directory index for obtaining a number of key information values pertaining to a particular printed circuit board assembly.

Abstract: A configuration system and method uses a program device containing configuration software for configuring applications to be executed by a processing system through the use of externally provided values corresponding to environment variables that are used to define an execution environment for all of the applications to be executed by the system. The configuration system is used to establish a plurality of configuration file sources to be used in configuring applications wherein the files define a plurality of different operational levels. Each configuration file stores the values representative of a corresponding number of configurable items defining the environment for executing the applications. The values of each level has a pre-established override capability over the values of other levels.

Abstract: Integrated circuit component with terminals for connection to an external communication channel or bus, serial test interface and a configuration register whose content defines operational modes of the integrated circuit, in which the configuration register is loaded with a default configuration, applied externally, through the serial test interface in the course of an initializing phase in which a reset signal applied to the integrated circuit is asserted and in which the default configuration is modifiable via SW or FW, through the external communication channel when the reset signal is deasserted.

Abstract: A multihomed host system is configured with independent front end processor transport providers, each having its own network protocol stack and each being connected to a different TCP/IP network or subnetwork or to different portions of the same network which in turn connects to an internetnetwork. The host system software includes a TCP/IP Transport Agent located between a sockets interface and the host system's input/output supervisor and driver facilities. The TCP/IP Transport Agent is enhanced to include a FEP Multihoming and Routing component for providing a multihoming capability. The FEP Multihoming and Routing component utilizes a plurality of components which are configured from the same administrator supplied configuration and static routing information furnished to the FEPs for configuring their respective TCP/IP stack facilities.

Abstract: A host system includes a multicache system configured within a host system's memory which has a plurality of local and central cache systems used for storing information being utilized by a plurality of processes running on the system. The central cache system includes an obsolete code management (OCM) component that operates to detect and remove obsolete entries stored within the central cache system. The OCM component operates to remove obsolete code from all the caches when events cause such obsolescence, e.g., data definition language (DDL) statements are executed. In certain situations, by being able to perform such operations during DDL statement processing, the OCM component further enhances overall system operation.

Abstract: A host system includes a multicache system configured within the host system's memory which has a plurality of local and central cache systems used for storing information being utilized by a plurality of processes running on the system. Persistent shared memory is used to store control structure information entries required for operating central cache systems for substantially long periods of time in conjunction with the local caches established for the processes. Such entries includes a descriptor value for identifying a directory control structure and individual sets of descriptors for identifying a group of control structures defining those components required for operating the configured central cache systems. The cache directory structure is used for defining the name of each configured central cache system and for providing an index value identifying the particular set of descriptors associated therewith.

Abstract: The main storage of a system includes a virtual memory space containing a plurality of virtual frame buffers for storing information transferred from disk storage shared by a number of virtual processes being executed by the system. An associated buffer table and aging mechanism includes a buffer table storing a plurality of buffer table entries associated with the corresponding number of virtual buffers used for controlling access thereto and an age table containing entries associated with the buffer table entries containing forward and backward age pointers linked together defining the relative aging of the virtual frame buffers from the most recently used to least recently used. Each buffer table entry has a frequency reference counter which maintains a reference count defining the number of times that its associated virtual buffer has been uniquely accessed by the virtual processes.

Abstract: A mapping between terminal presentation and a Graphical User Interface to an end user using a web browser is provided. The mapping representation is created to support a selected screen image sent from the application to the web browser. A generic interpretative applet and the screen mapping representation is forwarded to a web server and in turn is downloaded to a web browser using a well known protocol. The applet generates and processes messages in an acceptable presentation, e.g. IBM 3270 format, and exchanges those messages directly with a receiving application across a computer network, thereby reducing or eliminating message translation and traffic through intermediate applications and systems.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed.

Abstract: Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).

Abstract: A search mechanism improves the performance of a queue system including a queue for storing a plurality of data items and search mechanism by maintaining a key cache data structure having an array of entries, each of which have a key field and a pointer field. The key and pointer fields respectively of each cache entry are used for storing a key value of a different one of the enqueued data items of the queue and a pointer to that enqueued item. The key of each data item to be enqueued is used to generate an index value for accessing a location of the key cache array to obtain immediate access to the corresponding enqueued data item thereby reducing the search time for determining the proper point within the queue for inserting the data item to be added.

Abstract: In order to gather, store temporarily and efficiently deliver safestore information in a CPU having data manipulation circuitry including a register bank, first and second serially oriented safestore buffers are employed. At suitable times during the processing of information, a copy of the instantaneous contents of the register bank is transferred into the first safestore buffer. After a brief delay, a copy of the first safestore buffer is transferred into the second safestore buffer. If a call for a domain change (which might include a process change or a fault) is sensed, a safestore frame is sent to cache, and the first safestore buffer is loaded from he second safestore buffer rather than from the register bank.